メニュー
Place and route with nextpnr for open-source FPGA targets. Supports iCE40, ECP5, and Gowin devices. Example: "place and route for iCEBreaker", "run P&R targeting ice40"
デフォルトでは、最初にソースを確認する Prompt が選択されています。直接コマンドに切り替えるか、ローカルコピーをダウンロードすることもできます。
インストールを決める前に、SKILL.md と SkillsMP に表示されている付属ファイルをお読みください。
Codex または Claude でインストール この Prompt をコピーして Codex、Claude、または他のアシスタントに貼り付けると、Skill ページを確認してインストールできます。
直接コマンドでは確認用 Prompt が省略されます。実行前にソースを確認してください。
npx skills add https://github.com/codejunkie99/Gateflow-Plugin --skill gf-pnrコマンドは1行のまま表示されます。コピー前に横へスクロールして全体を確認してください。
ローカルで確認しますか？SkillsMP が現在取得できるファイルをダウンロードできます。
SKILL.md を表示中
| name | gf-pnr |
| description | Place and route with nextpnr for open-source FPGA targets. Supports iCE40, ECP5, and Gowin devices. Example: "place and route for iCEBreaker", "run P&R targeting ice40" |
| allowed-tools | ["Bash","Read","Write","Glob","AskUserQuestion"] |
| FPGA Family | Tool | Command |
|---|---|---|
| Lattice iCE40 | nextpnr-ice40 | nextpnr-ice40 --up5k --package sg48 --json synth.json --pcf constraints.pcf --asc output.asc |
| Lattice ECP5 | nextpnr-ecp5 | nextpnr-ecp5 --85k --package CABGA381 --json synth.json --lpf constraints.lpf --textcfg output.config |
| Gowin | nextpnr-gowin | nextpnr-gowin --device GW1NR-LV9QN88PC6/I5 --json synth.json --cst constraints.cst |
NOT Supported: Xilinx (use Vivado), Intel (use Quartus). For these, GateFlow generates TCL scripts instead.
which nextpnr-ice40 || which nextpnr-ecp5 || which nextpnr-gowin
If not found:
---GATEFLOW-RESULT---
STATUS: ERROR
DETAILS: nextpnr not installed. Install for place & route.
macOS: brew install nextpnr
Linux: see https://github.com/YosysHQ/nextpnr
---END-GATEFLOW-RESULT---
After P&R:
icepack output.asc output.binecppack output.config output.bit---GATEFLOW-RESULT---
STATUS: PASS | FAIL | ERROR
TIMING:
Fmax: 125.3 MHz
Slack: +2.1 ns
UTILIZATION:
LUTs: 142 / 5280 (2.7%)
FFs: 87 / 5280 (1.6%)
FILES: [output files]
DETAILS: [summary or timing violations]
---END-GATEFLOW-RESULT---
| Flag | Purpose |
|---|---|
--freq <mhz> | Target frequency |
--seed <n> / -r | RNG seed / randomize |
--opt-timing | Post-placement timing opt |
--report <file> | JSON timing/utilization |
--timing-allow-fail | Proceed despite violations |
--router2-heatmap <prefix> | Congestion heatmaps |
--placer heap | Heap placer (default) |
Devices: --lp1k, --lp8k, --hx1k, --hx8k, --up5k
Output: --asc <file> | Constraints: --pcf <file>
Full pipeline: yosys -p "synth_ice40 -json out.json" design.v && nextpnr-ice40 --hx8k --package ct256 --json out.json --pcf pins.pcf --asc out.asc && icepack out.asc out.bin
Devices: --12k, --25k, --45k, --85k
Output: --textcfg <file> | Constraints: --lpf <file>, --sdc <file>
Full pipeline: yosys -p "synth_ecp5 -json out.json" design.v && nextpnr-ecp5 --25k --package CABGA256 --json out.json --lpf pins.lpf --textcfg out.config && ecppack out.config out.bit
Device: --device <part> (e.g., GW1NR-LV9QN88PC6/I5)
Family: --vopt family=<fam> (for C-silicon, e.g., GW1N-9C)
Constraints: --vopt cst=<file> (mandatory)
Full pipeline: yosys -p "synth_gowin -json out.json" design.v && nextpnr-himbaechel --device GW1NR-LV9QN88PC6/I5 --vopt family=GW1N-9C --vopt cst=pins.cst --json out.json --write routed.json && gowin_pack -d GW1N-9C -o out.fs routed.json
--freq 0 for auto-determine, --freq N for target--opt-timing for post-placement optimization-r) for better placement--placer-heap-timingweight (20-50)--router2-tmg-ripup for timing-driven rerouting-nowidelut for ECP5 (big Fmax improvement)| Usage | Status |
|---|---|
| < 50% | Comfortable |
| 50-70% | Normal |
| 70-80% | Tight |
| > 80% | Warning: congestion likely |
| > 95% | May fail to route |
| Failure | Fix |
|---|---|
| Routing congestion | Larger device, optimize synth, different seed |
| Timing violations | Pipeline, --opt-timing, different seed |
| Placement failure | Check constraints, try --placer sa |
| Combinatorial loops | Break with register, or --ignore-loops |
set_io clk 21
set_io led[0] 99
set_frequency clk 48
LOCATE COMP "clk" SITE "P6";
IOBUF PORT "clk" IO_TYPE=LVCMOS33;
FREQUENCY PORT "clk" 48000000.0 HZ;
IO_LOC "clk" 52;
IO_PORT "clk" IO_TYPE=LVCMOS33;
GateFlow terminal console inspired by OpenClaw local TUI workflows. Shows workspace status, component inventory, tool health, map readiness, release readiness, and command shortcuts from one terminal surface.
GateFlow release readiness workflow. Validates plugin manifests, marketplace metadata, docs index coverage, root mirrors, release notes, and component counts before a version tag is created. Use when preparing, checking, or cutting a GateFlow plugin release.
FuseSoC build system integration for GateFlow. Generates .core files and drives synthesis/simulation through Edalize backends (Vivado, Quartus, open-source tools). Use when the user needs to create a FuseSoC core file, build with Edalize, or integrate RTL into a FuseSoC project.
SOC 職業分類に基づく
