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Analyze and fix clock domain crossing violations. Use when CDC violations appear, when auditing multi-clock designs, or when reviewing set_false_path and set_max_delay exceptions for safety.
Codex または Claude でインストール この Prompt をコピーして Codex、Claude、または他のアシスタントに貼り付けると、Skill ページを確認してインストールできます。
SOC 職業分類に基づく
Run a complete Vivado FPGA design flow from RTL sources to bitstream. Use when asked to synthesize, implement, build, or compile an FPGA design. Also handles project creation, checkpoint management, and run orchestration.
Author and audit Vivado XDC constraint files. Use when creating constraints, finding unconstrained paths, debugging timing exceptions, checking clock definitions, or auditing I/O delays for completeness.
Insert ILA and VIO debug cores into a Vivado design. Use when asked to add hardware debug probes, set up ILA trigger conditions, insert VIO for stimulus injection, or generate .ltx probeinfo files.
Create Pblock floorplan constraints in Vivado. Use when dealing with placement congestion, SSI multi-die devices, reconfigurable partitions (DFX), or when critical paths need physical locality.
Run a complete Vivado design flow: project creation, synthesis, implementation, bitstream. Use when asked to build, synthesize, implement, or compile an FPGA design from RTL sources.
Run Vivado implementation phases: opt_design, place_design, phys_opt_design, route_design. Use when asked to run implementation, choose implementation directives, or re-run specific implementation phases.
| name | vivado-cdc |
| version | 1.0.0 |
| description | Analyze and fix clock domain crossing violations. Use when CDC violations appear, when auditing multi-clock designs, or when reviewing set_false_path and set_max_delay exceptions for safety. |
| metadata | {"openclaw":{"requires":{"bins":["vivado"]},"emoji":"🔀"}} |
report_cdc -details -waived -file /tmp/vivaclaw_rpt/cdc_details.rpt
report_clock_interaction -delay_type min_max -significant_only -file /tmp/vivaclaw_rpt/clock_interaction.rpt
| Type | Classification | Action |
|---|---|---|
| A | Single-bit Control | 2-FF Sync + ASYNC_REG TRUE |
| B | Multi-bit Data Bus | FIFO/Handshake ONLY. Review Required. |
| C | Gray Counter | set_max_delay -datapath_only <period_dst> |
| D | FIFO Crossing | Verify depth/flags sync. |
| E | MUX Static Path | set_false_path (Static signals only). |
| F | Reset Crossing | Async assert, Sync deassert. |
set_clock_groups -asynchronous \
-group [get_clocks clk_a] \
-group [get_clocks clk_b]
report_synchronizer_mtbf -file /tmp/vivaclaw_rpt/mtbf.rpt
Target: >1e6 hours. If lower, increase sync chain depth to 3 FFs.
Every waived path must include a reason:
# CDC WAIVER | Type: <X> | Reason: <description> | Confirmed: VivaClaw