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Create Pblock floorplan constraints in Vivado. Use when dealing with placement congestion, SSI multi-die devices, reconfigurable partitions (DFX), or when critical paths need physical locality.
Codex または Claude でインストール この Prompt をコピーして Codex、Claude、または他のアシスタントに貼り付けると、Skill ページを確認してインストールできます。
SOC 職業分類に基づく
Run a complete Vivado FPGA design flow from RTL sources to bitstream. Use when asked to synthesize, implement, build, or compile an FPGA design. Also handles project creation, checkpoint management, and run orchestration.
Analyze and fix clock domain crossing violations. Use when CDC violations appear, when auditing multi-clock designs, or when reviewing set_false_path and set_max_delay exceptions for safety.
Author and audit Vivado XDC constraint files. Use when creating constraints, finding unconstrained paths, debugging timing exceptions, checking clock definitions, or auditing I/O delays for completeness.
Insert ILA and VIO debug cores into a Vivado design. Use when asked to add hardware debug probes, set up ILA trigger conditions, insert VIO for stimulus injection, or generate .ltx probeinfo files.
Run a complete Vivado design flow: project creation, synthesis, implementation, bitstream. Use when asked to build, synthesize, implement, or compile an FPGA design from RTL sources.
Run Vivado implementation phases: opt_design, place_design, phys_opt_design, route_design. Use when asked to run implementation, choose implementation directives, or re-run specific implementation phases.
| name | vivado-floorplan |
| version | 1.0.0 |
| description | Create Pblock floorplan constraints in Vivado. Use when dealing with placement congestion, SSI multi-die devices, reconfigurable partitions (DFX), or when critical paths need physical locality. |
| metadata | {"openclaw":{"requires":{"bins":["vivado"]},"emoji":"🗺️"}} |
Invoke floorplanning if congestion score > 5:
report_design_analysis -complexity -congestion -file /tmp/vivaclaw_rpt/congestion.rpt
create_pblock pblock_dsp_accel
add_cells_to_pblock [get_pblocks pblock_dsp_accel] [get_cells -hierarchical module_name/*]
resize_pblock [get_pblocks pblock_dsp_accel] -add {SLICE_X20Y20:SLICE_X40Y60}
set_property CONTAIN_ROUTING true [get_pblocks pblock_dsp_accel]
Pblocks must include specific resource columns (BRAM/DSP) if assigned cells use them.
resize_pblock [get_pblocks <pb>] -add {RAMB36_X2Y5:RAMB36_X3Y10}
Assign logic to a specific Super Logic Region:
resize_pblock [get_pblocks <pb>] -add [get_sites -of_objects [get_slrs SLR0]]
Constraint: High-speed buses crossing SLRs incur 1-3ns delay. Pipeline crossings.
set_property HD.RECONFIGURABLE true [get_cells <inst>]
create_pblock <pb>
add_cells_to_pblock <pb> [get_cells <inst>]
set_property SNAPPING_MODE ON [get_pblocks <pb>]
Check report_pblock for overlaps or overfilling.