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Create or explain fixed-format HSB FPGA_top.sv wrappers from validated HOLOLINK_def.svh files. Do not use for def generation or validation.
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npx skills add https://github.com/NVIDIA/skills --skill hsb-ip-create-topコマンドは1行のまま表示されます。コピー前に横へスクロールして全体を確認してください。
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Use when measuring Jetson Video Codec SDK or PyNvVideoCodec encode/decode throughput, comparing presets or surfaces, testing codec-worker capacity with authenticated samples and user media, or producing a documented clock-scaled or clock-and-resolution-scaled planning estimate when representative content is unavailable. Also use for Jetson video requests asking only for PSNR or SSIM results, to apply this performance skill's scope-only response.
Use when Jetson codec, profile, chroma, bit-depth, dimension, engine-count, or operational support must be reconciled using live SDK APIs, authenticated NVIDIA samples, and NVIDIA documentation. Also use for Jetson questions about Netflix, Widevine, or other DRM-protected streaming-service playback to apply the codec-scope boundary.
Use when executing and verifying Jetson Video Codec SDK or PyNvVideoCodec encode/decode, transcode, segmentation, container decode, AV1, or acceptance workflows with exact artifact handoffs.
| name | hsb-ip-create-top |
| author | Holoscan Team <holoscan-team@nvidia.com> |
| description | Create or explain fixed-format HSB FPGA_top.sv wrappers from validated HOLOLINK_def.svh files. Do not use for def generation or validation. |
| version | 0.1.0 |
| tags | ["holoscan","hsb","fpga","systemverilog","top-level"] |
| license | Apache-2.0 |
| compatibility | Targets HSB IP rev 16'h2604; backward-compatible with 16'h2603. Prefer live HSB IP source when available; warn on unknown revisions. Designed to work standalone or as a companion to hsb-ip-def. |
| metadata | {"author":"Holoscan Team <holoscan-team@nvidia.com>","team":"holoscan","domain":"fpga","vendor":"nvidia","tags":["holoscan","hsb","fpga","top-level","systemverilog"],"languages":["systemverilog"],"artifact":"FPGA_top.sv","source_artifact":"HOLOLINK_def.svh","hsb_ip_version":"16'h2604"} |
Create a fixed-format SystemVerilog top-level scaffold that instantiates HOLOLINK_top and declares the HSB-facing signals required by a validated HOLOLINK_def.svh.
This skill owns only the top-level scaffold around the HSB IP:
HOLOLINK_def.svh includeFPGA_top module shellHOLOLINK_top instantiationUse hsb-ip-def for HOLOLINK_def.svh generation and validation. Do not create or validate the defs file here.
HOLOLINK_def.svh path or pasted file content is required before generating FPGA_top.sv.HOLOLINK_top.sv source is preferred when source-sensitive port extraction is needed; bundled references cover known rev 16'h2604 and compatible rev 16'h2603.HOLOLINK_def.svh before creating FPGA_top.sv. If the user does not have one, invoke or direct them to hsb-ip-def first.HOLOLINK_top.sv as the source of truth for ports, directions, macro gates, and IP revision whenever it is available.references/fixed-format.md as the baked formatting and naming style. Do not inspect example top-level files just to confirm formatting during normal generation.FPGA_top module normally has no top-level ports.HOLOLINK_top under the active macro set.HOLOLINK_top port shapes exactly: keep packed vector widths before the signal name and unpacked interface-array dimensions after the signal name.references/fixed-format.md, including unpacked arrays for multi-interface *_tdata, *_tkeep, and *_tuser buses and the APB shape documented there.FPGA_top.sv, use generic wording such as "data manipulation behavior".Prefer live HSB IP source over bundled references whenever the user's workspace provides it. The bundled references describe known rev 16'h2604 and backward-compatible rev 16'h2603; live source is the authority for the checked-out IP.
When source is available:
<hsb-ip-root>/top/HOLOLINK_top.sv. Known roots include hw/nvcpu_dgx_fpga/vrtl/hololink/ and public-release fpga/nv_hsb_ip/.HOLOLINK_REV and HOLOLINK_BACKWARD_COMPAT_REV from HOLOLINK_top.sv.HOLOLINK_top module declaration to confirm port names, directions, widths, ordering, and ifdef/ifndef gates.When no source is available, use the bundled references as known-revision guidance and say the scaffold is based on the skill's supported HSB IP rev. If the user already authorized using the bundled known-rev port reference when no checkout is obvious, do a brief search of obvious roots and then proceed with bundled references instead of asking the live-source question.
If the source root is not obvious, ask conversationally in one turn:
Do you have a current HSB IP `HOLOLINK_top.sv` source checkout you want me to use for port extraction, or should I use the skill's bundled known-rev port reference?
Accept either a path or a "use bundled reference" answer.
Load only the reference needed for the user's task:
| File | When to load |
|---|---|
references/source-policy.md | Finding live HSB IP source, handling unknown revisions, or deciding source/reference precedence |
references/fixed-format.md | Generating or explaining the fixed FPGA_top.sv scaffold format |
references/handoff-contract.md | Standalone prerequisite handling or def-skill handoff behavior |
hsb-ip-def after a successful defs generation/validation, use Def-Skill Handoff.FPGA_top.sv, instantiate HOLOLINK_top, or make a top-level wrapper, use Standalone Create Top.Use this when the user invokes this skill directly.
Steps:
HOLOLINK_def.svh, or accept pasted content. If the user does not have a defs file, stop and direct them to hsb-ip-def to create and validate it first.hsb-ip-def validation. Do not proceed from an unvalidated defs file.references/source-policy.md and references/fixed-format.md.HOLOLINK_top port groups from live source when available.FPGA_top.sv in the fixed format. If writing a file, default filename is FPGA_top.sv unless the user provides a path.## Instructions; do not enumerate what is outside the scaffold's scope.Use this when hsb-ip-def has just completed a validated HOLOLINK_def.svh and the user chooses to create a matching top-level scaffold.
Steps:
hsb-ip-def.references/handoff-contract.md and references/fixed-format.md.FPGA_top.sv scaffold from the active defs macros and live HOLOLINK_top.sv when available.## Instructions. Do not enumerate what is outside the scaffold's scope.Use this when the user asks why a port or signal group appears, how macro settings affect the top scaffold, or how the skill handles IP revisions.
Steps:
HOLOLINK_top.sv when available. Otherwise load references/fixed-format.md.references/source-policy.md.hsb-ip-def.hsb-ip-def validation.Use hsb-ip-create-top to create an FPGA_top.sv scaffold from my validated HOLOLINK_def.svh. Use the bundled known-rev port reference if no HSB IP source checkout is obvious. Treat as Standalone Create Top, require the validated defs file, load references/source-policy.md and references/fixed-format.md, use bundled known-rev ports after a brief source search, and report the defs status, port-map source, and emitted signal groups.Create a top-level FPGA_top.sv wrapper for HSB, but I do not have a HOLOLINK_def.svh yet. Stop before generation, direct the user to hsb-ip-def, and ask for a validated defs file path or content before proceeding.Why does the generated FPGA_top.sv include different HSB signal groups depending on my HOLOLINK_def.svh macros? Treat as Explain, say that validated defs macros gate the HSB-facing signal groups and that the live HOLOLINK_top.sv port map wins when available; defer detailed macro semantics to hsb-ip-def.HOLOLINK_def.svh.HOLOLINK_def.svh files.