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.v/.sv 파일 수정, RTL 신호 추적, FSM 분석, 합성 에러 수정 시 호출. Trigger on: 'verilog', 'module', 'signal', 'fsm', 'synthesis', 'rtl', 'always', 'wire', 'reg', 'posedge', '합성', '신호', '상태머신'.
デフォルトでは、最初にソースを確認する Prompt が選択されています。直接コマンドに切り替えるか、ローカルコピーをダウンロードすることもできます。
インストールを決める前に、SKILL.md と SkillsMP に表示されている付属ファイルをお読みください。
Codex または Claude でインストール この Prompt をコピーして Codex、Claude、または他のアシスタントに貼り付けると、Skill ページを確認してインストールできます。
直接コマンドでは確認用 Prompt が省略されます。実行前にソースを確認してください。
npx skills add https://github.com/together2329/brian_hw --skill verilog-expertコマンドは1行のまま表示されます。コピー前に横へスクロールして全体を確認してください。
ローカルで確認しますか？SkillsMP が現在取得できるファイルをダウンロードできます。
Use before locked OAG RTL, TB, or evidence implementation dispatch when role-specific generated authoring packets must be compiled, audited, or passed to native subagents instead of raw user prose.
Use when OAG requirements or requirement atoms must be projected into independently checkable obligations and assume/guarantee contracts with behavior, cycle, scenario, scoreboard, assertion, or coverage proof refs.
Use when OAG hardware IP work needs lock-blocking product or design choices captured, seeded from a profile, audited, or kept separate from locked truth before requirements, RTL, TB, or closure.
SOC 職業分類に基づく
SKILL.md を表示中
| name | verilog-expert |
| description | .v/.sv 파일 수정, RTL 신호 추적, FSM 분석, 합성 에러 수정 시 호출. Trigger on: 'verilog', 'module', 'signal', 'fsm', 'synthesis', 'rtl', 'always', 'wire', 'reg', 'posedge', '합성', '신호', '상태머신'. |
| priority | 90 |
| activation | {"keywords":["verilog","systemverilog","rtl","hdl","synthesize","synthesis","timing","signal","module","always","reg","wire","posedge","negedge","fsm","state","clocking","iverilog","verilator","yosys","quartus","vivado","modelsim","axi","ahb","apb","pcie","wishbone","avalon","amba","fifo","counter","uart","spi","i2c","timer","pwm","clock","reset","async","synchronous","asynchronous","combinational","sequential","blocking","nonblocking","state machine","pipeline","handshake","신호","모듈","설계","검증","상태머신","클럭","리셋","동기","비동기","조합","순차","블로킹","넌블로킹"],"file_patterns":["*.v","*.sv"],"auto_detect":true} |
| requires_tools | ["analyze_verilog_module","find_signal_usage","rag_search","read_lines"] |
| related_skills | ["testbench-expert"] |
| Tool | When to use |
|---|---|
| rag_search(query, categories="verilog") | 신호/모듈 위치 찾기 (최우선) |
| read_lines(path, start, end) | RAG 결과 확인 — 반드시 실제 코드 읽기 |
| analyze_verilog_module(path, deep) | 모듈 전체 구조 분석 |
| find_signal_usage(signal, dir) | 신호 할당/사용처 추적 |
| grep_file(pattern, path) | 정확한 패턴 매칭 (fallback) |
| replace_in_file(path, old, new) | 코드 수정 (write_file 금지) |
| Situation | File |
|---|---|
| Signal tracing workflow | signal-tracing.md |
| Compilation error patterns | error-recovery.md |
| Detailed tool selection guide | tool-selection.md |