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Use when designing clock domain crossing architecture. Triggers on 'CDC', '跨时钟域', '时钟域', '同步策略', '多时钟', 'clock domain', '亚稳态', '双触发器'. Performs multi-clock domain partitioning, CDC signal identification and synchronization strategy design.
Codex または Claude でインストール この Prompt をコピーして Codex、Claude、または他のアシスタントに貼り付けると、Skill ページを確認してインストールできます。
SOC 職業分類に基づく
Autonomous iterative research loop. Takes a topic, runs web searches, fetches sources, synthesizes findings, and files everything into the wiki as structured pages. Based on Karpathy's autoresearch pattern: program.md configures objectives and constraints, the loop runs until depth is reached, output goes directly into the knowledge base. Triggers on: "/autoresearch", "autoresearch", "research [topic]", "deep dive into [topic]", "investigate [topic]", "find everything about [topic]", "research and file", "go research", "build a wiki on".
Visual layer of the wiki. Add images, text cards, PDFs, and wiki pages to Obsidian canvas files with auto-positioning inside zones. Integrates with /banana for image capture. Triggers on: /canvas, canvas new, canvas add image, canvas add text, canvas add pdf, canvas add note, canvas zone, canvas list, canvas from banana, add to canvas, put this on the canvas, open canvas, create canvas.
Use when running RTL lint checks. Triggers on 'lint', 'verilator', 'verible', 'spyglass', '语法检查', '可综合性', '组合环路', 'latch检查', 'rtl lint', 'lint检查'. Supports multiple EDA tools with auto-detection.
Use when processing vc-spyglass lint log output to resolve violations. Maps lint rules to JMTAG execution levels, proposes RTL fixes or generates waive files. Triggered by keywords like spyglass, lint log, lint violation, JMTAG, waive file, lint rules.
Use when generating comprehensive SDC timing constraints from FS/microarch documents. Triggers on '生成SDC', 'SDC约束', 'timing constraints', '时序约束文件', 'write SDC', 'SDC文件'. Produces production-quality SDC covering clocks, I/O, design rules, timing exceptions, and area/power constraints.
Use when running SpyGlass CDC checks on RTL. Triggers on 'cdc检查', 'cdc check', 'spyglass cdc', '跨时钟域检查', 'cdc验证', 'clock domain crossing', 'cdc setup', 'cdc_verify'. Generates SGDC constraints, runs CDC goals, produces violation reports.
| name | chip-cdc-architect |
| description | Use when designing clock domain crossing architecture. Triggers on 'CDC', '跨时钟域', '时钟域', '同步策略', '多时钟', 'clock domain', '亚稳态', '双触发器'. Performs multi-clock domain partitioning, CDC signal identification and synchronization strategy design. |
输出架构级的 CDC 设计方案与风险评估。
### CDC 架构决策
#### 时钟域列表
| 时钟域 | 频率 | 来源 | 备注 |
|--------|------|------|------|
#### CDC 信号与同步策略
| 信号名 | 位宽 | 源时钟域 | 目标时钟域 | 同步策略 | 深度/级数 | 风险等级 |
|--------|------|----------|------------|----------|-----------|----------|
#### 验证建议
- ...
示例 1：双时钟域 CDC 设计
用户：data_adpt 模块有两个时钟域，clk_core 500MHz 和 clk_axi 250MHz，帮我设计 CDC 方案
预期行为：
示例 2：CDC 风险评估
用户：检查 data_adpt 的 CDC 设计有没有风险，特别是那几个跨域的控制信号
预期行为：评估亚稳态传播风险，检查同步级数是否足够，给出 MTBF 估算
| 场景 | 触发条件 | 处理动作 |
|---|---|---|
| 时钟信息缺失 | FS 中未定义时钟域 | 暂停，列出需要的时钟信息（频率/来源/相位关系） |
| CDC 信号过多 | > 50 个跨域信号 | 分组输出，优先处理控制信号和关键数据通路 |
| 同步策略不确定 | 无法判断用 FIFO 还是握手 | 给出两种方案的对比表，用户选择 |
| MTBF 不满足 | 估算 MTBF < 目标 | 建议增加同步级数或改用更可靠的方案 |