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codejunkie99
GitHub 제작자 프로필

codejunkie99

11개 GitHub 저장소에서 수집된 97개 skills를 저장소 단위로 보여줍니다.

수집된 skills
97
저장소
11
업데이트
2026년 8월 18일
여기에는 상위 8개 저장소가 표시되며, 전체 저장소 목록은 아래에서 이어집니다.
저장소 탐색

저장소와 대표 skills

apology-crafter
작가·저자

Use when the user wants to craft a sincere, accountable apology in both written and spoken versions, without deflection. Triggers include "draft an apology", "how should I apologize", "say sorry to".

2026년 4월 26일
difficult-conversation-prep
인사 전문가

Use when the user wants to prepare for a hard conversation with empathetic-but-direct opening, defensiveness handling, and resolution paths. Triggers include "difficult conversation", "hard talk", "tough conversation prep".

2026년 4월 26일
elevator-pitch-builder
작가·저자

Use when the user wants three energy-level variants of an elevator pitch (bold, conversational, data-driven). Triggers include "elevator pitch", "pitch this product", "30 second pitch".

2026년 4월 26일
feedback-giver
인사 관리자총괄·운영 관리자

Use when the user wants to draft spoken feedback using observation/impact/expectation/support framework. Triggers include "give feedback", "feedback to my report", "performance feedback".

2026년 4월 26일
presentation-outliner
작가·저자

Use when the user wants a tight presentation outline with hook, problem, solution, evidence, objection handling, and clear CTA. Triggers include "outline a presentation", "talk outline", "structure my pitch deck".

2026년 4월 26일
data-interpreter
데이터 과학자

Use when the user wants plain-English interpretation of a dataset including patterns, surprises, and misleading aspects. Triggers include "analyze this data", "interpret these numbers", "what does this data mean".

2026년 4월 26일
research-synthesizer
기타 사회 과학자 및 관련 종사자

Use when the user has multiple research sources on a topic and wants genuine synthesis of themes, contradictions, and gaps — not separate summaries. Triggers include "synthesize this research", "compare these sources", "research synthesis".

2026년 4월 26일
survey-analyzer
시장조사 분석가·마케팅 전문가

Use when the user wants to analyze survey results for findings, consensus, division, surprises, and actionable recommendations. Triggers include "analyze survey", "survey results", "what does this survey show".

2026년 4월 26일
수집된 skill 40개 중 8개를 표시합니다.
gf-tui
소프트웨어 개발자

GateFlow terminal console inspired by OpenClaw local TUI workflows. Shows workspace status, component inventory, tool health, map readiness, release readiness, and command shortcuts from one terminal surface.

2026년 5월 21일
gf-release
소프트웨어 개발자

GateFlow release readiness workflow. Validates plugin manifests, marketplace metadata, docs index coverage, root mirrors, release notes, and component counts before a version tag is created. Use when preparing, checking, or cutting a GateFlow plugin release.

2026년 5월 20일
gf-fusesoc
전자 엔지니어(컴퓨터 제외)

FuseSoC build system integration for GateFlow. Generates .core files and drives synthesis/simulation through Edalize backends (Vivado, Quartus, open-source tools). Use when the user needs to create a FuseSoC core file, build with Edalize, or integrate RTL…

2026년 4월 15일
gf-learn
기타 중등 후 교사

SystemVerilog learning mode — generates exercises, reviews solutions, and teaches RTL design patterns. Use when the user wants to learn SystemVerilog, practice hardware design, get exercises, or understand verification methodology.

2026년 4월 15일
gf-router
전자 엔지니어(컴퓨터 제외)

Figures out what kind of digital hardware design task the user wants to do, then hands off to the right specialist. Use when the request is unclear, multi-step, or needs help deciding whether to simulate, synthesize, lint, or implement.

2026년 4월 15일
gf
전자 엔지니어(컴퓨터 제외)

Primary SystemVerilog/RTL orchestrator for GateFlow. Routes to specialist agents, runs verification, and iterates until working. Use when the user wants to create, test, fix, or implement any RTL design — FIFO, UART, AXI, state machines, or any digital…

2026년 4월 15일
gf-summary
전자 엔지니어(컴퓨터 제외)

Summarize Verilator, lint, or simulation output into a readable, actionable format. Use when the user wants to understand build output, lint errors, or simulation results from a Verilator or EDA tool run.

2026년 4월 15일
gf-architect
전자 엔지니어(컴퓨터 제외)

Codebase architect - Maps and documents SystemVerilog projects. This skill should be used when the user wants to understand a codebase structure, generate architecture documentation, or onboard to a new RTL project. Example requests: "map this codebase",…

2026년 4월 11일
수집된 skill 27개 중 8개를 표시합니다.
gateflow-behavior
소프트웨어 개발자

This skill should be used when the user is working on any SystemVerilog, Verilog, HDL, RTL, FPGA, or ASIC development task. Provides behavioral rules for GateFlow: auto-chain workflows, context-aware actions, and seamless tool execution without requiring…

2026년 2월 5일
systemverilog-rtl-design
소프트웨어 개발자

Provides RTL design patterns, synthesis guidelines, and coding templates. Use when the user mentions 'module design', 'FSM', 'state machine', 'pipeline', 'synthesizable', 'parameterize', 'parameter', 'localparam', 'clock domain', 'CDC', 'FIFO', 'register…

2026년 2월 5일
systemverilog-lint-fixing
소프트웨어 개발자

This skill should be used when the user mentions 'lint error', 'width mismatch', 'inferred latch', 'undriven signal', 'fix warnings', 'Verilator error', 'WIDTHTRUNC', 'BLKSEQ', or asks to 'check my code' or 'find errors'. Provides error-specific fix patterns…

2026년 2월 5일
systemverilog-testbench-patterns
소프트웨어 품질 보증 분석가·테스터

This skill should be used when the user asks to 'write a testbench', 'test this module', 'add assertions', 'create test stimulus', 'verify the design', 'add clock generation', or 'write a self-checking test'. Provides testbench templates, clock/reset…

2026년 2월 5일
systemverilog-verification
소프트웨어 품질 보증 분석가·테스터

Provides verification methodology, SVA assertion patterns, coverage techniques, and testbench templates. Use when the user mentions 'testbench', 'assertion', 'SVA', 'property', 'sequence', 'coverage', 'covergroup', 'coverpoint', 'bins', 'cross coverage',…

2026년 2월 5일
vcd-waveform-analysis
소프트웨어 개발자

This skill should be used when the user mentions 'waveform', 'VCD file', 'simulation results', 'signal trace', 'debug the output', 'what happened in sim', 'show me the waves', or 'analyze timing'. Provides VCD parsing, clock detection, anomaly identification,…

2026년 2월 5일
systemverilog-development
소프트웨어 개발자

This skill should be used when the user asks to 'design a module', 'write SystemVerilog', 'implement an FSM', 'create a pipeline', or works with .sv/.svh/.v/.vh files. Provides modern SV conventions, coding patterns, and synthesizability guidance.

2026년 2월 5일
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