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codejunkie99
GitHub creator profile

codejunkie99

Repository-level view of 76 collected skills across 5 GitHub repositories, including approximate occupation coverage.

skills collected
76
repositories
5
occupation fields
4
updated
2026-05-21
repository explorer

Repositories and representative skills

#001
prompt-skills
40 skills151updated 2026-04-26
53% of creator
apology-crafter
작가·저자

Use when the user wants to craft a sincere, accountable apology in both written and spoken versions, without deflection. Triggers include "draft an apology", "how should I apologize", "say sorry to".

2026-04-26
difficult-conversation-prep
인사 전문가

Use when the user wants to prepare for a hard conversation with empathetic-but-direct opening, defensiveness handling, and resolution paths. Triggers include "difficult conversation", "hard talk", "tough conversation prep".

2026-04-26
elevator-pitch-builder
작가·저자

Use when the user wants three energy-level variants of an elevator pitch (bold, conversational, data-driven). Triggers include "elevator pitch", "pitch this product", "30 second pitch".

2026-04-26
feedback-giver
인사 관리자총괄·운영 관리자

Use when the user wants to draft spoken feedback using observation/impact/expectation/support framework. Triggers include "give feedback", "feedback to my report", "performance feedback".

2026-04-26
presentation-outliner
작가·저자

Use when the user wants a tight presentation outline with hook, problem, solution, evidence, objection handling, and clear CTA. Triggers include "outline a presentation", "talk outline", "structure my pitch deck".

2026-04-26
data-interpreter
데이터 과학자

Use when the user wants plain-English interpretation of a dataset including patterns, surprises, and misleading aspects. Triggers include "analyze this data", "interpret these numbers", "what does this data mean".

2026-04-26
research-synthesizer
기타 사회 과학자 및 관련 종사자

Use when the user has multiple research sources on a topic and wants genuine synthesis of themes, contradictions, and gaps — not separate summaries. Triggers include "synthesize this research", "compare these sources", "research synthesis".

2026-04-26
survey-analyzer
시장조사 분석가·마케팅 전문가

Use when the user wants to analyze survey results for findings, consensus, division, surprises, and actionable recommendations. Triggers include "analyze survey", "survey results", "what does this survey show".

2026-04-26
Showing top 8 of 40 collected skills in this repository.
#002
Gateflow-Plugin
27 skills8611updated 2026-05-21
36% of creator
gf-tui
소프트웨어 개발자

GateFlow terminal console inspired by OpenClaw local TUI workflows. Shows workspace status, component inventory, tool health, map readiness, release readiness, and command shortcuts from one terminal surface.

2026-05-21
gf-release
소프트웨어 개발자

GateFlow release readiness workflow. Validates plugin manifests, marketplace metadata, docs index coverage, root mirrors, release notes, and component counts before a version tag is created. Use when preparing, checking, or cutting a GateFlow plugin release.

2026-05-20
gf-fusesoc
소프트웨어 개발자

FuseSoC build system integration for GateFlow. Generates .core files and drives synthesis/simulation through Edalize backends (Vivado, Quartus, open-source tools). Use when the user needs to create a FuseSoC core file, build with Edalize, or integrate RTL into a FuseSoC project.

2026-04-15
gf-learn
소프트웨어 개발자

SystemVerilog learning mode — generates exercises, reviews solutions, and teaches RTL design patterns. Use when the user wants to learn SystemVerilog, practice hardware design, get exercises, or understand verification methodology.

2026-04-15
gf-router
소프트웨어 개발자

Figures out what kind of digital hardware design task the user wants to do, then hands off to the right specialist. Use when the request is unclear, multi-step, or needs help deciding whether to simulate, synthesize, lint, or implement.

2026-04-15
gf
컴퓨터 하드웨어 엔지니어

Primary SystemVerilog/RTL orchestrator for GateFlow. Routes to specialist agents, runs verification, and iterates until working. Use when the user wants to create, test, fix, or implement any RTL design — FIFO, UART, AXI, state machines, or any digital hardware module.

2026-04-15
gf-summary
소프트웨어 개발자

Summarize Verilator, lint, or simulation output into a readable, actionable format. Use when the user wants to understand build output, lint errors, or simulation results from a Verilator or EDA tool run.

2026-04-15
gf-architect
건축가(조경 및 선박 제외)

Codebase architect - Maps and documents SystemVerilog projects. This skill should be used when the user wants to understand a codebase structure, generate architecture documentation, or onboard to a new RTL project. Example requests: "map this codebase", "document the architecture", "show module hierarchy"

2026-04-11
Showing top 8 of 27 collected skills in this repository.
#003
gateflow-cli
7 skills30updated 2026-02-05
9.2% of creator
gateflow-behavior
소프트웨어 개발자

This skill should be used when the user is working on any SystemVerilog, Verilog, HDL, RTL, FPGA, or ASIC development task. Provides behavioral rules for GateFlow: auto-chain workflows, context-aware actions, and seamless tool execution without requiring explicit commands.

2026-02-05
systemverilog-rtl-design
소프트웨어 개발자

Provides RTL design patterns, synthesis guidelines, and coding templates. Use when the user mentions 'module design', 'FSM', 'state machine', 'pipeline', 'synthesizable', 'parameterize', 'parameter', 'localparam', 'clock domain', 'CDC', 'FIFO', 'register file', 'always_ff', 'always_comb', 'generate', or asks about synthesis-related coding.

2026-02-05
systemverilog-lint-fixing
소프트웨어 개발자

This skill should be used when the user mentions 'lint error', 'width mismatch', 'inferred latch', 'undriven signal', 'fix warnings', 'Verilator error', 'WIDTHTRUNC', 'BLKSEQ', or asks to 'check my code' or 'find errors'. Provides error-specific fix patterns for SystemVerilog lint issues.

2026-02-05
systemverilog-testbench-patterns
소프트웨어 품질 보증 분석가·테스터

This skill should be used when the user asks to 'write a testbench', 'test this module', 'add assertions', 'create test stimulus', 'verify the design', 'add clock generation', or 'write a self-checking test'. Provides testbench templates, clock/reset patterns, and assertion guidance.

2026-02-05
systemverilog-verification
소프트웨어 품질 보증 분석가·테스터

Provides verification methodology, SVA assertion patterns, coverage techniques, and testbench templates. Use when the user mentions 'testbench', 'assertion', 'SVA', 'property', 'sequence', 'coverage', 'covergroup', 'coverpoint', 'bins', 'cross coverage', 'constrained random', 'randomize', 'constraint', 'simulate', 'waveform', 'VCD', '$display', '$finish', or 'self-checking'.

2026-02-05
vcd-waveform-analysis
소프트웨어 개발자

This skill should be used when the user mentions 'waveform', 'VCD file', 'simulation results', 'signal trace', 'debug the output', 'what happened in sim', 'show me the waves', or 'analyze timing'. Provides VCD parsing, clock detection, anomaly identification, and signal tracing techniques.

2026-02-05
systemverilog-development
소프트웨어 개발자

This skill should be used when the user asks to 'design a module', 'write SystemVerilog', 'implement an FSM', 'create a pipeline', or works with .sv/.svh/.v/.vh files. Provides modern SV conventions, coding patterns, and synthesizability guidance.

2026-02-05
#005
avids-essential-skills
1 skills31updated 2026-04-06
1.3% of creator
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