folsie/anlogic-fpga-workflow

anlogic-code-design

安路 FPGA 代码设计 skill。Use when: 需要把已分析清楚的需求落成一致风格的 RTL，规范接口、简化 primitive 引脚连接、保持可扩展可移植，并形成交给 anlogic-testbench 的设计交付。

원문 언어: 다국어 혼합

anlogic-create-bitstream

安路 FPGA bitstream 生成 skill。Use when: 需要执行、排查或审阅 TD 的 bitgen、setup_debugger、export_bitgen_param、export_bid，确认从已放行的 pr.db 到 .bit/.bid/.bitgen_param.f 的边界、输入、交付物和放行条件，判断问题属于 bitgen 参数、前置 pr.db、probe/debugger 还是文件/权限，并避免把 route 或下载交付误塞进 bitstream 阶段。

원문 언어: 중국어

anlogic-modelsim

Use when Anlogic FPGA verification inputs are ready and Codex needs to run ModelSim, organize `run.do` plus `wave.do`, preserve waveform artifacts, export `.vcd` from `.wlf`, and produce a pass/fail/block conclusion that is valid for downstream waveform…

원문 언어: 영어

anlogic-needs-analysis

Use when Anlogic FPGA work still needs requirement decomposition, device and resource judgment, interface analysis, module partitioning, timing/data-flow planning, or upstream design direction. This stage must decide when the requirement is clear enough to…

원문 언어: 영어

anlogic-place-route

安路 FPGA 布局布线 flow skill。Use when: 需要执行、排查或审阅 TD 物理实现阶段的 opt_place、opt_route，确认从 gate.db 到 pr.db 的边界、输入、交付物和放行条件，判断问题属于 place、route、hold 修复、时钟/拥塞/DRC，避免把综合问题或 bitgen 交付误塞进物理实现阶段。

원문 언어: 중국어

anlogic-project-creation

Use when Anlogic FPGA verification is already complete and Codex needs to create the TD project from validated design inputs, constraints, IP, and wrappers. This stage begins only after `anlogic-modelsim`, `anlogic-wave-signal-analyzer`, and…

원문 언어: 영어

anlogic-synthesis

安路 FPGA 综合 flow skill。Use when: 需要执行、排查或审阅 TD 综合阶段的 read_design、opt_rtl、opt_gate，确认综合阶段的输入、边界、交付物和放行条件，判断问题属于工程入口、RTL/IP、约束还是 primitive 映射，并避免把 place、route、bitgen 的等待和动作误塞进综合阶段。

원문 언어: 중국어

anlogic-testbench

安路 FPGA testbench skill。Use when: 需要消费 anlogic-code-design 的设计交付，生成 stimulus、monitor/checker、期望结果和通过判定口径，并把可运行输入交给 anlogic-modelsim。

원문 언어: 중국어