hardware-motivated-noise-modeling

# Hardware-Motivated Noise Modeling for QEC Benchmarking ## Problem Uniform depolarizing noise model assumes homogeneous error rates, failing to capture heterogeneity, asymmetries, and correlations of real quantum devices where Pauli, measurement, and spatio-temporal errors are not weakly coupled. ## Core Mechanism ### Structured Noise Families 1. **Pauli bias**: Asymmetric X/Y/Z error rates reflecting device-specific error channels 2. **Measurement bias**: Different readout error rates for |0> vs |1> states 3. **Spatial non-uniformity**: Position-dependent error rates across qubit array 4. **Spatio-temporal correlations**: Time-varying error patterns with spatial structure ### Tripartite Interplay Analysis 1. Evaluate logical primitives (memory, lattice surgery, transversal gates) 2. Measure performance across noise model × primitive × decoder combinations 3. Each combination yields qualitatively distinct results ### Benchmark Protocol 1. Specify noise model parameters matching target hardware 2. Construct logical primitives using surface code operations 3. Run simulation with decoder matched to noise structure 4. Compare logical error rates and fault-tolerance thresholds ## When to Use - Evaluating QEC protocols under realistic conditions - Designing fault-tolerant quantum architectures - Hardware-aware co-design of quantum systems - Benchmarking logical computation (not just passive memory) ## Pitfalls - Ignoring noise structure leads to inaccurate FT performance predictions - Decoder choice must match noise structure for fair comparison - Active computation benchmarks differ fundamentally from memory benchmarks - Structured noise simulation is more computationally expensive ## Verification - Logical error rates should decrease with code distance (FT threshold behavior) - Different noise models should yield different optimal decoder choices - Results should reproduce known analytical thresholds in simple cases