메뉴
Use when exploring PPA design space for optimal solutions. Triggers on '设计空间', 'DSE', '帕累托', 'pareto', 'PPA探索', '方案比选', 'trade-off', 'design space'. Performs Area-Performance-Power 3D exploration to find Pareto-optimal set.
Codex 또는 Claude로 설치 이 Prompt를 복사해 Codex, Claude 또는 다른 어시스턴트에 붙여 넣으면 Skill 페이지를 검토하고 설치를 진행할 수 있습니다.
SOC 직업 분류 기준
Autonomous iterative research loop. Takes a topic, runs web searches, fetches sources, synthesizes findings, and files everything into the wiki as structured pages. Based on Karpathy's autoresearch pattern: program.md configures objectives and constraints, the loop runs until depth is reached, output goes directly into the knowledge base. Triggers on: "/autoresearch", "autoresearch", "research [topic]", "deep dive into [topic]", "investigate [topic]", "find everything about [topic]", "research and file", "go research", "build a wiki on".
Visual layer of the wiki. Add images, text cards, PDFs, and wiki pages to Obsidian canvas files with auto-positioning inside zones. Integrates with /banana for image capture. Triggers on: /canvas, canvas new, canvas add image, canvas add text, canvas add pdf, canvas add note, canvas zone, canvas list, canvas from banana, add to canvas, put this on the canvas, open canvas, create canvas.
Use when running RTL lint checks. Triggers on 'lint', 'verilator', 'verible', 'spyglass', '语法检查', '可综合性', '组合环路', 'latch检查', 'rtl lint', 'lint检查'. Supports multiple EDA tools with auto-detection.
Use when processing vc-spyglass lint log output to resolve violations. Maps lint rules to JMTAG execution levels, proposes RTL fixes or generates waive files. Triggered by keywords like spyglass, lint log, lint violation, JMTAG, waive file, lint rules.
Use when generating comprehensive SDC timing constraints from FS/microarch documents. Triggers on '生成SDC', 'SDC约束', 'timing constraints', '时序约束文件', 'write SDC', 'SDC文件'. Produces production-quality SDC covering clocks, I/O, design rules, timing exceptions, and area/power constraints.
Use when running SpyGlass CDC checks on RTL. Triggers on 'cdc检查', 'cdc check', 'spyglass cdc', '跨时钟域检查', 'cdc验证', 'clock domain crossing', 'cdc setup', 'cdc_verify'. Generates SGDC constraints, runs CDC goals, produces violation reports.
| name | chip-design-space-explorer |
| description | Use when exploring PPA design space for optimal solutions. Triggers on '设计空间', 'DSE', '帕累托', 'pareto', 'PPA探索', '方案比选', 'trade-off', 'design space'. Performs Area-Performance-Power 3D exploration to find Pareto-optimal set. |
在 Area-Performance-Power 三维空间中进行设计空间探索（DSE），寻找帕累托最优解集。
### DSE 结果（帕累托前沿）
| 设计点 | 配置摘要 | 延迟 (ns) | 吞吐 (GB/s) | 面积 (kGates) | 功耗 (mW) | 帕累托最优 |
|--------|----------|-----------|-------------|---------------|-----------|------------|
| A | 3级流水线, 64b总线 | 5.0 | 12.8 | 80 | 15 | ✓ |
| B | 5级流水线, 128b总线 | 3.2 | 25.6 | 150 | 28 | ✓ |
### 推荐设计点
**推荐：B**
- 理由：...
- 风险：...
示例 1：FIFO 深度 DSE
用户：帮我探索 data_adpt 的 FIFO 深度设计空间，突发量 32 beats，生产者速率 1B/cycle，消费者速率 0.5B/cycle
预期行为：
示例 2：流水线级数 DSE
用户：data_adpt 的处理路径可以做 3/4/5 级流水线，帮我比选最优方案
预期行为：枚举 3 个设计点，计算延迟/吞吐/面积/功耗，标注帕累托最优解
| 场景 | 触发条件 | 处理动作 |
|---|---|---|
| 设计旋钮未定义 | 用户未指定探索变量 | 列出常见旋钮（流水线级数/并行度/缓存/总线宽度/频率），用户选择 |
| 评估模型缺失 | 无法估算 PPA | 使用经验公式 + 标注"待综合验证"，建议 DSE 后跑综合确认 |
| 设计点过多 | > 100 个组合 | 使用拉丁超立方采样减少到 20-30 个代表点 |
| 帕累托前沿为空 | 所有设计点被支配 | 检查约束条件是否过紧，建议放宽 1-2 个约束重新探索 |