Arcadia-1

Crawl and analyze post-layout parasitic netlists without running SPICE. Answers "what's the effective resistance from node A to node B across this massive R mesh?", "inside the VREFN mesh, which device pins are electrically farthest apart?", "which nets have…

ADC characterization orchestrator in the analog-agents project. Takes simulated/measured ADC output, produces the standard specs bundle (SNDR/SFDR/THD/ENOB, INL/DNL, FOM, NTF where applicable) as a verifier-report, and hands off back to the design/sizing…

Pre-simulation review and Spectre simulation verification for analog circuits. Reviews circuit netlist and testbench, runs simulation, produces margin report. Use after analog-design completes a netlist.

Move, clone, package, archive, split, or reorganize Cadence Virtuoso cells and libraries at the design-data level. Use this skill whenever the user wants to: copy a TB to another library, reproduce a sim independently in a fresh library, hand off a design,…

Self-evolution engine for analog-agents. Reviews completed design sessions to extract lessons, discover new anti-patterns, propose checklist additions, and refine agent prompts. Run after design convergence or project completion. TRIGGER on: "evolve", "what…

MANDATORY — MUST load this skill when the user mentions: OTA, ADC, PLL, comparator, bandgap, LDO, amplifier, opamp, or any analog/mixed-signal IC design task. Full analog design pipeline: spec -> architecture -> design -> verify -> deliver. Orchestrates…

Audit analog circuit netlists for correctness, quality, and risks. Supports both pre-layout (schematic) and post-layout (extracted) netlists. Post-layout mode filters massive parasitic netlists before auditing. Works without EDA. TRIGGER on: "audit", "review…

Explore analog design space without simulation. Compare topologies, sweep parameters with hand calculations, find theoretical limits and Pareto tradeoffs. Use for architecture selection, initial sizing, or understanding design space before committing to EDA…

Two-stage CMOS operational amplifier simulation skill. Use when the user wants to simulate or size a Miller-compensated two-stage op amp with PMOS differential input pair, NMOS current-mirror first-stage load, NMOS common-source second stage, PMOS…

Five-transistor OTA simulation and analysis skill. Use when the user wants to simulate or size a classic 5T CMOS OTA: NMOS differential input pair, PMOS current-mirror active load, and NMOS tail current transistor. Supports ngspice DC transfer, AC…

PTM 180nm PMOS-pass LDO regulator simulation, sizing, and analysis skill. Use this skill whenever the user wants to: (1) simulate or re-run LDO DC/AC/noise/transient analyses in ngspice, (2) plot loop gain, PSRR, output impedance, load-step response, noise…

Bootstrapped sampling switch simulation and analysis skill for SAR ADC design. Use when the user wants to: (1) simulate a bootstrap switch with ngspice (180nm PTM, VDD=1.8V), (2) verify the bootstrap mechanism — gate voltage tracks Vin+VDD, (3) compare…

StrongArm dynamic comparator simulation and analysis skill. Use this skill whenever the user wants to simulate, analyse, or learn about a StrongArm (or similar dynamic) comparator. Trigger on any of: (1) run a comparator transient simulation in ngspice, (2)…

Bridge to remote Cadence Virtuoso via Python API. TRIGGER when user mentions: Virtuoso, Maestro, ADE, CIW, SKILL, layout, schematic, cellview, OCEAN, or any Cadence EDA operation.

Run Cadence Spectre simulations remotely via virtuoso-bridge: upload netlists, execute, parse PSF results. TRIGGER when the user wants to run a SPICE/Spectre simulation from a netlist file, do transient/AC/PSS/pnoise analysis outside Virtuoso GUI, parse PSF…

Semantic cleanup and curation of Spectre/SPICE transistor netlists for analog review or reusable reference circuits. Use when Codex needs to understand generated ADE/PEX netlists, split DUT/testbench/run decks, optionally strip layout-derived MOS tail…

Black-box optimization of design parameters using TuRBO or scipy. TRIGGER when the user wants to optimize, tune, size, sweep, or explore a design space to meet specs. This includes circuit sizing (W/L, bias, passives), finding optimal operating points,…

Sky130A open PDK workflow for ngspice-based analog simulation. Use when an agent needs to install or locate Sky130A via Volare/open_pdks, run process-corner PVT simulations, run process Monte Carlo or mismatch-aware smoke tests, instantiate sky130_fd_pr…

ngspice simulation tutorial and template skill. Provides nine standard simulation examples: (1) Transient — RC charging voltage and current; (2) DC — NMOS Id-Vds family curves; (3) AC — RC low-pass filter frequency response; (4) Noise — RC filter output noise…

Complete PTM (Predictive Technology Model) MOSFET model library from mec.umn.edu/ptm, covering all nodes: bulk conventional 180/130/90/65nm, bulk HP/LP 45/32/22nm (BSIM4), and PTM-MG multi-gate FinFET 7/10/14/16/20nm (BSIM-CMG, HP + LSTP). No manual downloads…

gm/ID transistor characterization and design methodology, based on ngspice + Python. Two independent workflows: (1) Characterization — generates three standard curve sets for any MOSFET model: gate capacitance (Cgg/Cgs/Cgd/Cgb vs Vgs), gm/ID four-quadrant…

Verilog-A language authoring guidance for writing, reviewing, or explaining .va behavioral modules. Use for Verilog-A syntax and semantics: modules and ports, disciplines and natures, analog blocks, branch access, contributions, events, parameters, arrays,…

How to use the EVAS Verilog-A behavioral simulator (pip package: evas-sim). Use this skill whenever the user wants to simulate a Verilog-A (.va) model, run a Spectre (.scs) netlist, check simulation feasibility, install evas-sim, or read simulation output…

Compile Verilog-A device models with OpenVAF and simulate them in ngspice via OSDI. Use this skill whenever the user wants to: compile a .va file, run a Verilog-A model in ngspice, use OpenVAF, load an OSDI model, test a compact device model, or set up the…

Router skill for using ADCToolbox from Python. Trigger when a task involves: computing or plotting spectra (SNDR, SFDR, ENOB, THD) from ADC output, fitting a sine to measured aout, calibrating SAR weights (weight_sine / weight_sine_lite), generating synthetic…

Maintainer-only guide for editing the ADCToolbox repository itself. Use this skill only when changing source, exports, examples, tests, packaging, or the bundled skills under `python/src/adctoolbox/_bundled_skills/skills/`. Do not use it for ordinary library…

Use when visible/public EVAS simulation is allowed for a Verilog-A voltage-domain model. Covers when EVAS applies, how to run evas-sim, minimal Spectre .scs syntax, save/output files, and common EVAS setup failures. Does not teach Verilog-A authoring.

Use when writing, fixing, or reviewing Verilog-A behavioral modules. Focuses on syntax, module/port discipline, state/event modeling, transition outputs, vector handling, and EVAS/Spectre portability. Does not provide circuit-specific recipes or simulation…

Use ngspice with the Razavi-Bench Sky130 model bundle when a task has a concrete quantity worth probing. Provides workflows for operating-point checks, small-signal extraction, and simple AC/transient sanity tests. Use simulation selectively as evidence;…

Use this skill for SAR ADC system design and all its key building blocks. Covers: SAR ADC architecture, CDAC operation and switching schemes, sync/async SAR logic, top-plate vs bottom-plate sampling, noise and ENOB budgeting, redundancy, PVT, metastability,…

Use when working with EVAS/evas-sim: installing or running the EVAS Verilog-A behavioral simulator, checking whether a voltage-domain Verilog-A/Spectre testbench can run in EVAS, verifying or building the required evas-rust core, or interpreting EVAS outputs…

Manage author profiles for this Hugo/Wowchemy site. Use when adding or updating members, syncing content/en/authors and content/zh/authors, fixing avatar files, or adjusting People widget user_groups and author metadata.