| name | dbnn-spike-classification |
| description | DBNN (Deep Binarized Neural Network) for hardware-efficient neural spike classification with multiplier-free inference. Achieves 98.7% accuracy with 0.014 mm² area and 122 nW power at 20 kHz. Uses sign-controlled accumulation and bit-wise logic for implantable brain-computer interfaces. Activation: DBNN, spike sorting, binarized neural network, brain-computer interface, FPGA implementation, ASIC design, neural decoding, implantable devices. |
| trigger_words | ["DBNN spike sorting","binarized neural network","spike classification","multiplier-free inference","implantable BCI","FPGA spike sorter","ASIC neural decoder","hardware-efficient spike","sign-controlled accumulation","bit-wise logic neural"] |
| arxiv_id | 2607.05590 |
| paper_title | DBNN: Neural Spike Classification Using a Deep Binarized Neural Network |
| authors | (Multiple authors) |
| date | 2026-07-06T00:00:00.000Z |
DBNN: Neural Spike Classification Using a Deep Binarized Neural Network
Overview
DBNN is a hardware-oriented deep binarized neural network for neural spike sorting that achieves 98.7% classification accuracy with extremely low hardware cost: 0.014 mm² silicon area and 122 nW power consumption at 20 kHz. The architecture uses multiplier-free inference dominated by sign-controlled accumulation and bit-wise logic, making it ideal for implantable brain-computer interfaces.
Paper: arXiv:2607.05590
Date: July 6, 2026
Core Innovation
Binarized Architecture for Ultra-Low Power
Traditional neural networks require expensive multiply-accumulate operations. DBNN replaces these with:
- Sign-controlled accumulation: Only add/subtract operations
- Bit-wise logic: AND, OR, XOR for feature extraction
- Fixed-point output: No floating-point arithmetic
This enables multiplier-free inference with dramatic power savings.
Hardware Efficiency
| Metric | Value |
|---|
| Accuracy | 98.7% |
| Silicon area | 0.014 mm² |
| Power consumption | 122 nW @ 20 kHz |
| FPGA resources | 828 ALMs, 1023 registers, 0 DSP blocks |
| Compute latency | 0.01 ms per spike (528 cycles @ 50 MHz) |
Architecture
Network Structure
Input (16 samples) → Hidden1 (256 neurons) → Hidden2 (256 neurons) → Output (3 classes)
- Input: Compact 16-sample spike waveforms
- Hidden layers: 2 binarized layers with 256 neurons each
- Output: Fixed-point layer for classification
- Total parameters: 16-256-256-3 (extremely compact)
Binarization Strategy
Weights: {-1, +1} stored as single bits
Activations: {-1, +1} computed via sign function
Inference:
output = sign(W · sign(input))
All multiplications replaced with:
