菜单
Assemble normalized requirements, the microarchitecture spec, generated RTL, and static audit summaries into one front-end handoff package. Use this skill whenever the block-level RTL planning flow needs one deterministic output that can feed downstream DV planning.
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基于 SOC 职业分类
Extract a source-grounded, AI-readable textual design view from HDL source, parser output, MCP tool output, or model reasoning. Use this skill when the user needs Verilog, SystemVerilog, VHDL, or proprietary hardware description language normalized into a reusable design view for downstream analysis flows such as timing, lint, CDC, RDC, formal planning, or DV planning. Prefer UHDM text for SystemVerilog/Verilog when available, AST JSON when UHDM is not available, and explicit model-derived views only when no tool evidence exists.
Analyze an HDL design view or visible RTL for pre-synthesis timing risk by estimating combinational logic depth on register-to-register and boundary timing paths. Use this skill when the user already has a UHDM text dump, AST JSON, source-grounded textual design view, or small visible RTL block and asks for critical paths, deep combinational logic, reg-to-reg timing risk, or pre-synthesis timing feedback. This skill is analysis-only; use an HDL-design-view extraction skill or flow when parser/tool/MCP selection, source-language normalization, or design-view generation is required.
Read an approved microarchitecture specification and emit synthesizable SystemVerilog with requirement traceability. Use this skill whenever the flow moves from block architecture into concrete RTL implementation.
Review synthesizable SystemVerilog for static RTL issues such as inferred latches, reset mismatches, width hazards, and multi-driver structure. Use this skill whenever generated RTL needs a deterministic front-end lint audit before CDC, RDC, or timing review.
Normalize a block-level design brief into deterministic requirements, explicit PPA targets, and open intake questions. Use this skill whenever the user provides high-level microarchitectural intent and the workflow must capture power, performance, and area before specification or RTL work begins.
Turn normalized block requirements into a Markdown microarchitecture specification with requirement traceability and targeted diagrams. Use this skill whenever the workflow needs a deterministic architecture document before RTL generation.
| name | block-rtl-package-assembler |
| description | Assemble normalized requirements, the microarchitecture spec, generated RTL, and static audit summaries into one front-end handoff package. Use this skill whenever the block-level RTL planning flow needs one deterministic output that can feed downstream DV planning. |
Merge the front-end planning artifacts into one block-level RTL handoff package.
Scope: block or small IP. This is a package assembly skill, not a DV or physical implementation flow.
Apply these repo rules before analysis and output generation:
../../rules/common/evidence-grounding.md../../rules/common/output-discipline.md../../rules/arch/requirements-traceability.md../../rules/arch/ppa-capture.mdRead the normalized requirements, spec artifacts, RTL design artifacts, and audit reports, then perform these steps:
REQ-NNN requirement namespace throughout the final package.block-dv-plan.Produce a single YAML document:
design:
top_module: event_counter
brief_summary: "Programmable event counter with optional interrupt threshold."
rtl_files:
- rtl/event_counter.sv
requirements:
- id: REQ-001
title: count qualified input events
category: function
priority: must
source: user
description: "The block increments a stored count when event_valid is asserted."
acceptance_criteria: "With counting enabled, each qualified event increments count_value by one."
ppa_targets:
performance:
target: "600"
units: "MHz"
priority: "primary"
status: numeric
power:
target: "minimize dynamic power"
units: null
priority: "secondary"
status: qualitative
area:
target: "small control block"
units: null
priority: "secondary"
status: qualitative
spec:
artifact_path: artifacts/microarchitecture/event_counter.md
requirements_trace:
- requirement_id: REQ-001
spec_sections:
- overview
- datapath
coverage: full
diagrams: []
rtl:
source_files:
- path: rtl/event_counter.sv
module: event_counter
language: systemverilog
content: "module event_counter; endmodule"
rtl_modules:
- name: event_counter
role: top
clocks:
- clk
resets:
- rst_n
description: "Counts qualified events and exposes the stored count."
traceability:
- requirement_id: REQ-001
spec_sections:
- datapath
rtl_files:
- rtl/event_counter.sv
rtl_signals:
- event_valid
- count_value
audit_summary:
lint:
total_findings: 0
blocking_findings: 0
cdc:
violations: 0
highest_severity: none
rdc:
violations: 0
highest_severity: none
timing:
hard_or_worse_paths: 0
deepest_path_depth: 4
ready_for_dv_handoff: true
unresolved: []
downstream_handoff:
recommended_flow: block-dv-plan
top_module: event_counter
rtl_files:
- rtl/event_counter.sv
design_intent_markdown: artifacts/microarchitecture/event_counter.md
notes: "Use the generated microarchitecture spec as the design-intent brief for the downstream DV planning flow."
summary:
total_requirements: 1
total_rtl_files: 1
total_blocking_issues: 0
total_unresolved: 0