菜单
Turn normalized block requirements into a Markdown microarchitecture specification with requirement traceability and targeted diagrams. Use this skill whenever the workflow needs a deterministic architecture document before RTL generation.
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基于 SOC 职业分类
Extract a source-grounded, AI-readable textual design view from HDL source, parser output, MCP tool output, or model reasoning. Use this skill when the user needs Verilog, SystemVerilog, VHDL, or proprietary hardware description language normalized into a reusable design view for downstream analysis flows such as timing, lint, CDC, RDC, formal planning, or DV planning. Prefer UHDM text for SystemVerilog/Verilog when available, AST JSON when UHDM is not available, and explicit model-derived views only when no tool evidence exists.
Analyze an HDL design view or visible RTL for pre-synthesis timing risk by estimating combinational logic depth on register-to-register and boundary timing paths. Use this skill when the user already has a UHDM text dump, AST JSON, source-grounded textual design view, or small visible RTL block and asks for critical paths, deep combinational logic, reg-to-reg timing risk, or pre-synthesis timing feedback. This skill is analysis-only; use an HDL-design-view extraction skill or flow when parser/tool/MCP selection, source-language normalization, or design-view generation is required.
Read an approved microarchitecture specification and emit synthesizable SystemVerilog with requirement traceability. Use this skill whenever the flow moves from block architecture into concrete RTL implementation.
Review synthesizable SystemVerilog for static RTL issues such as inferred latches, reset mismatches, width hazards, and multi-driver structure. Use this skill whenever generated RTL needs a deterministic front-end lint audit before CDC, RDC, or timing review.
Normalize a block-level design brief into deterministic requirements, explicit PPA targets, and open intake questions. Use this skill whenever the user provides high-level microarchitectural intent and the workflow must capture power, performance, and area before specification or RTL work begins.
Assemble normalized requirements, the microarchitecture spec, generated RTL, and static audit summaries into one front-end handoff package. Use this skill whenever the block-level RTL planning flow needs one deterministic output that can feed downstream DV planning.
| name | microarchitecture-spec-author |
| description | Turn normalized block requirements into a Markdown microarchitecture specification with requirement traceability and targeted diagrams. Use this skill whenever the workflow needs a deterministic architecture document before RTL generation. |
Generate one Markdown microarchitecture specification from normalized block requirements.
Scope: block or small IP. This is a specification skill, not an RTL or signoff tool.
Apply these repo rules before analysis and output generation:
../../rules/common/evidence-grounding.md../../rules/common/output-discipline.md../../rules/arch/requirements-traceability.md../../rules/arch/ppa-capture.md../../rules/arch/diagram-selection.mdRead the normalized requirements and perform these steps:
Produce a single YAML document:
design:
top_module: event_counter
brief_summary: "Programmable event counter with optional interrupt threshold."
requirements_trace:
- requirement_id: REQ-001
spec_sections:
- overview
- datapath
coverage: full
artifact:
path: artifacts/microarchitecture/event_counter.md
format: markdown
spec_markdown: |
# Event Counter Microarchitecture
## Overview
This block counts qualified input events and raises an optional threshold interrupt.
diagrams:
- tool: blockdiag
title: block partitioning
purpose: block_diagram
artifact_path: artifacts/microarchitecture/diagrams/event_counter_blockdiag.diag
content: "blockdiag { counter_if -> counter_core -> irq_logic; }"
unresolved:
- item: threshold clear policy
reason: "The intake does not define whether irq clears automatically or only by software."
blocking: true
requirement_ids:
- REQ-001
summary:
total_traced_requirements: 1
total_diagrams: 1
total_unresolved: 1