菜单
Plan assertion candidates for a block-level DV effort from objectives and RTL evidence. Use this skill whenever the user wants reset, protocol, state, data-integrity, or error property candidates that are grounded in visible behavior rather than speculative timing assumptions.
用 Codex 或 Claude 帮你安装 复制这段 Prompt，粘贴到 Codex、Claude 或其他助手里，让它检查 Skill 页面并帮你完成安装。
基于 SOC 职业分类
Extract a source-grounded, AI-readable textual design view from HDL source, parser output, MCP tool output, or model reasoning. Use this skill when the user needs Verilog, SystemVerilog, VHDL, or proprietary hardware description language normalized into a reusable design view for downstream analysis flows such as timing, lint, CDC, RDC, formal planning, or DV planning. Prefer UHDM text for SystemVerilog/Verilog when available, AST JSON when UHDM is not available, and explicit model-derived views only when no tool evidence exists.
Analyze an HDL design view or visible RTL for pre-synthesis timing risk by estimating combinational logic depth on register-to-register and boundary timing paths. Use this skill when the user already has a UHDM text dump, AST JSON, source-grounded textual design view, or small visible RTL block and asks for critical paths, deep combinational logic, reg-to-reg timing risk, or pre-synthesis timing feedback. This skill is analysis-only; use an HDL-design-view extraction skill or flow when parser/tool/MCP selection, source-language normalization, or design-view generation is required.
Read an approved microarchitecture specification and emit synthesizable SystemVerilog with requirement traceability. Use this skill whenever the flow moves from block architecture into concrete RTL implementation.
Review synthesizable SystemVerilog for static RTL issues such as inferred latches, reset mismatches, width hazards, and multi-driver structure. Use this skill whenever generated RTL needs a deterministic front-end lint audit before CDC, RDC, or timing review.
Normalize a block-level design brief into deterministic requirements, explicit PPA targets, and open intake questions. Use this skill whenever the user provides high-level microarchitectural intent and the workflow must capture power, performance, and area before specification or RTL work begins.
Assemble normalized requirements, the microarchitecture spec, generated RTL, and static audit summaries into one front-end handoff package. Use this skill whenever the block-level RTL planning flow needs one deterministic output that can feed downstream DV planning.
| name | sva-candidate-planner |
| description | Plan assertion candidates for a block-level DV effort from objectives and RTL evidence. Use this skill whenever the user wants reset, protocol, state, data-integrity, or error property candidates that are grounded in visible behavior rather than speculative timing assumptions. |
Plan block-level assertion candidates that a DV or formal engineer could implement.
Scope: block or small IP. This is a planning skill, not automatic SVA generation.
Apply these repo rules before analysis and output generation:
../../rules/common/evidence-grounding.md../../rules/common/output-discipline.md../../rules/dv/objective-traceability.md../../rules/dv/assertion-classification.mdRead the DV objectives and RTL verification surface, then perform these steps:
../../rules/dv/assertion-classification.md.Produce a single YAML document:
design:
top_module: command_fsm
assertions:
- id: SVA-001
title: illegal command raises error
objective_ids:
- OBJ-003
class: error
source: both
bind_target: command_fsm
description: "When cmd_valid carries an unsupported opcode, error_flag asserts on the next state update."
summary:
total_assertions: 3
by_class:
reset: 1
protocol: 1
state: 0
data_integrity: 0
error: 1