菜单
Build a block-level, UVM-centric DV test matrix from objectives and RTL surface information. Use this skill whenever the user wants a greenfield UVM environment recommendation, prioritized test scenarios, and justified monitors, scoreboards, reference models, or virtual sequences.
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基于 SOC 职业分类
Extract a source-grounded, AI-readable textual design view from HDL source, parser output, MCP tool output, or model reasoning. Use this skill when the user needs Verilog, SystemVerilog, VHDL, or proprietary hardware description language normalized into a reusable design view for downstream analysis flows such as timing, lint, CDC, RDC, formal planning, or DV planning. Prefer UHDM text for SystemVerilog/Verilog when available, AST JSON when UHDM is not available, and explicit model-derived views only when no tool evidence exists.
Analyze an HDL design view or visible RTL for pre-synthesis timing risk by estimating combinational logic depth on register-to-register and boundary timing paths. Use this skill when the user already has a UHDM text dump, AST JSON, source-grounded textual design view, or small visible RTL block and asks for critical paths, deep combinational logic, reg-to-reg timing risk, or pre-synthesis timing feedback. This skill is analysis-only; use an HDL-design-view extraction skill or flow when parser/tool/MCP selection, source-language normalization, or design-view generation is required.
Read an approved microarchitecture specification and emit synthesizable SystemVerilog with requirement traceability. Use this skill whenever the flow moves from block architecture into concrete RTL implementation.
Review synthesizable SystemVerilog for static RTL issues such as inferred latches, reset mismatches, width hazards, and multi-driver structure. Use this skill whenever generated RTL needs a deterministic front-end lint audit before CDC, RDC, or timing review.
Normalize a block-level design brief into deterministic requirements, explicit PPA targets, and open intake questions. Use this skill whenever the user provides high-level microarchitectural intent and the workflow must capture power, performance, and area before specification or RTL work begins.
Assemble normalized requirements, the microarchitecture spec, generated RTL, and static audit summaries into one front-end handoff package. Use this skill whenever the block-level RTL planning flow needs one deterministic output that can feed downstream DV planning.
| name | uvm-test-matrix-planner |
| description | Build a block-level, UVM-centric DV test matrix from objectives and RTL surface information. Use this skill whenever the user wants a greenfield UVM environment recommendation, prioritized test scenarios, and justified monitors, scoreboards, reference models, or virtual sequences. |
Plan a block-level UVM environment and prioritized test matrix.
Scope: block or small IP. This is a planning skill, not UVM code generation.
Apply these repo rules before analysis and output generation:
../../rules/common/evidence-grounding.md../../rules/common/output-discipline.md../../rules/dv/objective-traceability.md../../rules/dv/uvm-component-selection.md../../rules/dv/stimulus-prioritization.mdRead the DV objectives and RTL verification surface, then perform these steps:
active or passive using
../../rules/dv/uvm-component-selection.md.Produce a single YAML document:
design:
top_module: status_fifo
env:
bench_style: greenfield_uvm
agents:
- name: write_agent
interface: write_side
mode: active
justification: "The bench must drive writes to exercise fill, overflow, and status behavior."
monitors:
- name: read_monitor
interface: read_side
justification: "Read-side activity must be observed for ordering and underflow checks."
scoreboards:
- name: fifo_order_scoreboard
compares: "Expected FIFO order against read data and level updates."
justification: "Data ordering cannot be checked by signal legality alone."
reference_models:
- name: fifo_reference_model
scope: "Golden queue model for occupancy and data order."
virtual_sequences:
- name: reset_fill_drain_vseq
objective_ids:
- OBJ-001
- OBJ-002
description: "Coordinates reset, burst writes, and burst reads."
tests:
- id: TEST-001
title: fifo reset and empty behavior
objective_ids:
- OBJ-001
stimulus: directed
checkers:
- fifo_order_scoreboard
priority: must
description: "Reset the FIFO and verify empty status, read gating, and clean level initialization."
summary:
total_tests: 3
by_priority:
must: 2
should: 1
could: 0