职业分类
电气工程师
描述
Maestro (ADE Assembler) session management and simulation. Use when: running simulations via Maestro, configuring tests/analyses/outputs, updating design variables, reading results.
更新
deanyou/virtuoso-cli
SkillsMP 已收集 deanyou/virtuoso-cli 中的 43 个 Skill。打开任一 Skill 可查看来源和详情。
- 最近记录的来源活动
- SkillsMP 收录数据更新
- 已收集 skills
- 43
- GitHub 星标
- 30
- GitHub Forks
- 9
这个仓库中的 skills
4 个职业分类 · 已分类 100%
已展示 40 / 43 个已收集 Skill。
skill
职业分类
描述
更新
职业分类
电子工程师（非计算机）
描述
Amplifier design copilot — topology selection, sizing via gm/Id lookup tables, PVT corner validation, and process-portable design. Use when designing amplifiers (OTA, opamp, comparator), selecting topology from specs, sizing transistors, or characterizing a…
原文语言：英语
更新
职业分类
电子工程师（非计算机）
描述
Explore Virtuoso cellviews - list libraries, cells, instances, nets, layers, and hierarchy. Use when browsing a design, understanding circuit topology, or inspecting layout/schematic contents.
原文语言：英语
更新
职业分类
电子工程师（非计算机）
描述
Bayesian optimization for circuit auto-tuning — closed-loop optimizer where Codex acts as the BO engine. Sweeps gm/Id + L parameters, runs Spectre, scores against specs, and iterates. Supports progressive PVT corners. Use when optimizing circuit sizing,…
原文语言：英语
更新
职业分类
电子工程师（非计算机）
描述
gm/Id methodology for analog IC design — transistor sizing via lookup table approach. Use when designing amplifiers, current mirrors, OTAs, or any analog circuit where you need to determine W/L from specs (GBW, gain, noise). Also use when the user mentions…
更新
职业分类
电子工程师（非计算机）
描述
Maestro (ADE Assembler) session management and simulation. Use when: running simulations via Maestro, configuring tests/analyses/outputs, reading results. Detailed API docs see `references/maestro-skill-api.md`.
原文语言：英语
更新
职业分类
电子工程师（非计算机）
描述
Fix Ocean SKILL simulation failures after schematic edits. Use when: (1) run() returns nil in <1s with no spectre.out, (2) createNetlist() returns nil, (3) sim results are all nil after changing W/L to design variables, (4) netlist file was deleted or is…
原文语言：英语
更新
职业分类
电子工程师（非计算机）
描述
Generate Virtuoso schematics from topology descriptions via vcli schematic commands. Use when: (1) user wants to draw/create a schematic in Virtuoso, (2) user says "draw the OTA" or "create the schematic", (3) after sizing is complete and ready to build the…
原文语言：英语
更新
职业分类
电子工程师（非计算机）
描述
Extract waveform measurements from Virtuoso simulation results. Use when measuring voltage, current, gm, gm/Id, bandwidth, settling time, or any simulation metric.
原文语言：英语
更新
职业分类
电子工程师（非计算机）
描述
Visualize Virtuoso simulation results as matplotlib charts. Use after: (1) sim sweep — line plot of measurements vs swept variable, (2) sim corner — grouped bar chart across PVT corners, (3) sim measure — horizontal bar of scalar measurements, (4) AC/Bode…
原文语言：英语
更新
职业分类
电子工程师（非计算机）
描述
Run circuit simulation (DC, tran, AC) on Virtuoso. Use when executing Spectre simulation, running analysis, or checking simulation results.
原文语言：英语
更新
职业分类
电子工程师（非计算机）
描述
Set up Virtuoso simulation with Ocean SKILL. Use when configuring simulator, design target, model files, or design variables before running simulation.
原文语言：英语
更新
职业分类
电子工程师（非计算机）
描述
Run parameter sweeps and PVT corner simulations on Virtuoso. Use when sweeping design variables, running corner analysis, or characterizing circuits across operating conditions.
原文语言：英语
更新
职业分类
电子工程师（非计算机）
描述
Execute SKILL code on Virtuoso. Use when running SKILL expressions, querying cellview data, listing libraries/cells, or interacting with Virtuoso programmatically.
原文语言：英语
更新
职业分类
电子工程师（非计算机）
描述
Critical SKILL language gotchas when integrating with shell/IPC in Cadence Virtuoso. Use when: (1) ipcBeginProcess exits with state=127 (command not found), (2) sh() returns unexpected values like "t" instead of command output, (3) trying to capture shell…
原文语言：英语
更新
职业分类
电子工程师（非计算机）
描述
Spec-driven analog circuit design — decompose system specs into block/transistor-level requirements, validate feasibility via simulation, and iterate. Use when defining amplifier specs, checking if specs are achievable, decomposing system requirements to…
原文语言：英语
更新
职业分类
电子工程师（非计算机）
描述
Critical Spectre netlist-mode gotchas for standalone simulation (no Virtuoso ADE). Use when: (1) writing Spectre testbench .scs files with `simulator lang=spectre`, (2) noise analysis shows absurd values (megavolts of noise) — oprobe topology is wrong, (3)…
原文语言：英语
更新
职业分类
电子工程师（非计算机）
描述
Connect to Virtuoso via SSH tunnel or local bridge. Use when setting up Virtuoso connection, starting the bridge, or troubleshooting connectivity issues.
原文语言：英语
更新
职业分类
电子工程师（非计算机）
描述
Design, write, and debug Verilog-A behavioral models for Cadence Virtuoso/Spectre simulation. Use when creating Verilog-A modules (voltage sources, behavioral models, testbench stimuli, ideal components), debugging Spectre simulation errors with Verilog-A, or…
原文语言：英语
更新
职业分类
软件开发工程师
描述
Connect to Virtuoso via SSH tunnel or local bridge. Use when setting up Virtuoso connection, starting the bridge, or troubleshooting connectivity issues.
原文语言：英语
更新
职业分类
电气工程师
描述
Import P&R (Genus + Innovus) products into Virtuoso: GDS layout, Verilog schematic/symbol, power labels, and label restyling. Four-step pipeline driven entirely from vcli skill exec — no Python bridge or GUI required. Use when: (1) user wants to pull a routed…
原文语言：英语
更新
职业分类
软件开发工程师
描述
Execute SKILL code on Virtuoso. Use when running SKILL expressions, querying cellview data, listing libraries/cells, or interacting with Virtuoso programmatically.
原文语言：英语
更新
职业分类
软件开发工程师
描述
Read-only diagnostics for stuck Virtuoso state via `vcli diag ...`. Use when: (1) a cellview won't open and you suspect `.cdslck` lock conflicts, (2) "why is this view held by someone?" — find the holder without deleting anything, (3) a modal dialog has…
原文语言：英语
更新
职业分类
电气工程师
描述
Run circuit simulation (DC, tran, AC) on Virtuoso. Use when executing Spectre simulation, running analysis, or checking simulation results.
原文语言：英语
更新
职业分类
电子工程师（非计算机）
描述
Generate Virtuoso schematics from topology descriptions via vcli schematic commands. Use when: (1) user wants to draw/create a schematic in Virtuoso, (2) user says "draw the OTA" or "create the schematic", (3) after sizing is complete and ready to build the…
原文语言：英语
更新
职业分类
软件开发工程师
描述
Read Maestro/ADE simulation output values directly from PSF binary files — no Virtuoso GUI or bridge required. Parses maestro.sdb + active.state XML to extract output expressions, resolves the PSF directory from history.sdb, evaluates Ocean-style expressions…
原文语言：英语
更新
职业分类
软件开发工程师
描述
Evolve skills from vcli session history. Use when: (1) user says "根據歷史進化技能" / "evolve skills from history" / "覆盤技能", (2) after a debugging session to capture what went wrong, (3) periodic skill maintenance to close knowledge gaps revealed by real usage. Reads…
原文语言：英语
更新
职业分类
软件开发工程师
描述
Critical SKILL language gotchas when integrating with shell/IPC in Cadence Virtuoso. Use when: (1) ipcBeginProcess exits with state=127 (command not found), (2) sh() returns unexpected values like "t" instead of command output, (3) trying to capture shell…
原文语言：英语
更新
职业分类
电子工程师（非计算机）
描述
Bayesian optimization for circuit auto-tuning — closed-loop optimizer where Claude acts as the BO engine. Sweeps gm/Id + L parameters, runs Spectre, scores against specs, and iterates. Supports progressive PVT corners. Use when optimizing circuit sizing,…
原文语言：英语
更新
职业分类
电子工程师（非计算机）
描述
Port circuit simulation setups from one PDK or process technology to another. Use this skill whenever migrating Maestro/ADE sessions, Ocean setup scripts, or Spectre netlists to a different foundry or process node — for example SMIC 28nm to TSMC 40nm, a PDK…
原文语言：英语
更新
职业分类
软件开发工程师
描述
Design, write, and debug Verilog-A behavioral models for Cadence Virtuoso/Spectre simulation. Use when creating Verilog-A modules (voltage sources, behavioral models, testbench stimuli, ideal components), debugging Spectre simulation errors with Verilog-A, or…
原文语言：英语
更新
职业分类
电子工程师（非计算机）
描述
Amplifier design copilot — topology selection, sizing via gm/Id lookup tables, PVT corner validation, and process-portable design. Use when designing amplifiers (OTA, opamp, comparator), selecting topology from specs, sizing transistors, or characterizing a…
原文语言：英语
更新
职业分类
软件开发工程师
描述
Explore Virtuoso cellviews - list libraries, cells, instances, nets, layers, and hierarchy. Use when browsing a design, understanding circuit topology, or inspecting layout/schematic contents.
原文语言：英语
更新
职业分类
电子工程师（非计算机）
描述
gm/Id methodology for analog IC design — transistor sizing via lookup table approach. Use when designing amplifiers, current mirrors, OTAs, or any analog circuit where you need to determine W/L from specs (GBW, gain, noise). Also use when the user mentions…
更新
职业分类
电子工程师（非计算机）
描述
Fix Ocean SKILL simulation failures after schematic edits. Use when: (1) run() returns nil in <1s with no spectre.out, (2) createNetlist() returns nil, (3) sim results are all nil after changing W/L to design variables, (4) netlist file was deleted or is…
原文语言：英语
更新
职业分类
电子工程师（非计算机）
描述
Extract waveform measurements from Virtuoso simulation results. Use when measuring voltage, current, gm, gm/Id, bandwidth, settling time, or any simulation metric.
原文语言：英语
更新
职业分类
软件开发工程师
描述
Visualize Virtuoso simulation results as matplotlib charts. Use after: (1) sim sweep — line plot of measurements vs swept variable, (2) sim corner — grouped bar chart across PVT corners, (3) sim measure — horizontal bar of scalar measurements, (4) AC/Bode…
原文语言：英语
更新
职业分类
电子工程师（非计算机）
描述
Set up Virtuoso simulation with Ocean SKILL. Use when configuring simulator, design target, model files, or design variables before running simulation.
原文语言：英语
更新
职业分类
电子工程师（非计算机）
描述
Run parameter sweeps and PVT corner simulations on Virtuoso. Use when sweeping design variables, running corner analysis, or characterizing circuits across operating conditions.
原文语言：英语
更新
职业分类
电子工程师（非计算机）
描述
Spec-driven analog circuit design — decompose system specs into block/transistor-level requirements, validate feasibility via simulation, and iterate. Use when defining amplifier specs, checking if specs are achievable, decomposing system requirements to…
原文语言：英语
更新
已展示 40 / 43 个已收集 Skill。