菜单
Run a complete Vivado FPGA design flow from RTL sources to bitstream. Use when asked to synthesize, implement, build, or compile an FPGA design. Also handles project creation, checkpoint management, and run orchestration.
用 Codex 或 Claude 帮你安装 复制这段 Prompt，粘贴到 Codex、Claude 或其他助手里，让它检查 Skill 页面并帮你完成安装。
基于 SOC 职业分类
Analyze and fix clock domain crossing violations. Use when CDC violations appear, when auditing multi-clock designs, or when reviewing set_false_path and set_max_delay exceptions for safety.
Author and audit Vivado XDC constraint files. Use when creating constraints, finding unconstrained paths, debugging timing exceptions, checking clock definitions, or auditing I/O delays for completeness.
Insert ILA and VIO debug cores into a Vivado design. Use when asked to add hardware debug probes, set up ILA trigger conditions, insert VIO for stimulus injection, or generate .ltx probeinfo files.
Create Pblock floorplan constraints in Vivado. Use when dealing with placement congestion, SSI multi-die devices, reconfigurable partitions (DFX), or when critical paths need physical locality.
Run a complete Vivado design flow: project creation, synthesis, implementation, bitstream. Use when asked to build, synthesize, implement, or compile an FPGA design from RTL sources.
Run Vivado implementation phases: opt_design, place_design, phys_opt_design, route_design. Use when asked to run implementation, choose implementation directives, or re-run specific implementation phases.
| name | vivado-flow |
| version | 1.0.0 |
| description | Run a complete Vivado FPGA design flow from RTL sources to bitstream. Use when asked to synthesize, implement, build, or compile an FPGA design. Also handles project creation, checkpoint management, and run orchestration. |
| metadata | {"openclaw":{"requires":{"bins":["vivado"]},"alwaysActive":false,"emoji":"🔁"}} |
Drives end-to-end: project creation → synthesis → opt → place → phys_opt → route → bitstream.
Confirm before starting:
vivado is on PATH: which vivadoxcvu9p-flgb2104-2-i)# Create in-memory project (no .xpr written to disk unless needed)
create_project vivaclaw_proj /tmp/vivaclaw_proj -part <PART> -force
# Add sources
read_verilog [glob <rtl_dir>/*.v]
read_verilog -sv [glob <rtl_dir>/*.sv]
read_vhdl [glob <rtl_dir>/*.vhd]
read_xdc <constraints.xdc>
set_property top <TOP_MODULE> [current_fileset]
update_compile_order -fileset sources_1
synth_design \
-top <TOP_MODULE> \
-part <PART> \
-directive <SYNTH_DIRECTIVE> \
-flatten_hierarchy rebuilt \
-fsm_extraction auto
write_checkpoint -force /tmp/vivaclaw_post_synth.dcp
report_timing_summary -file /tmp/vivaclaw_synth_timing.rpt
report_utilization -file /tmp/vivaclaw_synth_util.rpt
opt_design -directive <OPT_DIRECTIVE>
write_checkpoint -force /tmp/vivaclaw_post_opt.dcp
place_design -directive <PLACE_DIRECTIVE>
write_checkpoint -force /tmp/vivaclaw_post_place.dcp
phys_opt_design -directive <PHYSOPT_DIRECTIVE>
route_design -directive <ROUTE_DIRECTIVE>
write_checkpoint -force /tmp/vivaclaw_post_route.dcp
After route, extract WNS and TNS:
grep -E "WNS|TNS|WHS" /tmp/vivaclaw_route_timing.rpt | head -20
If WNS < 0: invoke vivado-timing skill. Do not proceed to bitstream.
Only run after:
report_drc shows zero CRITICAL errorsreport_drc -file /tmp/vivaclaw_drc.rpt
# Parse: if "CRITICAL" errors found → STOP, report to user
write_bitstream -force /tmp/vivaclaw_output.bit
If a post-route DCP exists and the user wants to skip re-running:
open_checkpoint /tmp/vivaclaw_post_route.dcp
After every Vivado call, scan stdout for:
ERROR: → stop, report
CRITICAL WARNING:→ evaluate, may stop
WNS.*(-[\d\.]+) → timing violation, invoke timing skill