菜单
Insert ILA and VIO debug cores into a Vivado design. Use when asked to add hardware debug probes, set up ILA trigger conditions, insert VIO for stimulus injection, or generate .ltx probeinfo files.
用 Codex 或 Claude 帮你安装 复制这段 Prompt，粘贴到 Codex、Claude 或其他助手里，让它检查 Skill 页面并帮你完成安装。
基于 SOC 职业分类
| name | vivado-debug |
| version | 1.0.0 |
| description | Insert ILA and VIO debug cores into a Vivado design. Use when asked to add hardware debug probes, set up ILA trigger conditions, insert VIO for stimulus injection, or generate .ltx probeinfo files. |
| metadata | {"openclaw":{"requires":{"bins":["vivado"]},"emoji":"🔬"}} |
Check BRAM availability. Each ILA uses BRAM:
Samples * ProbeWidth / 18432 = BRAM Blocks
Abort if utilization > 85%.
| Frequency | Depth |
|---|---|
| <100 MHz | 4096+ |
| 100-250 MHz | 2048 |
| >250 MHz | 1024 |
create_debug_core u_ila_0 ila
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property port_width 1 [get_debug_ports u_ila_0/clk]
connect_debug_port u_ila_0/clk [get_nets sys_clk]
set_property port_width 8 [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {data[*]}]]
create_debug_core u_vio_0 vio
set_property C_PROBE_OUT0_WIDTH 1 [get_debug_cores u_vio_0]
connect_debug_port u_vio_0/probe_out0 [get_nets reset_vio]
implement_debug_cores
route_design
write_bitstream debug_run.bit
write_debug_probes -force debug_run.ltx
Note: .bit and .ltx must be used together in Hardware Manager.
Run a complete Vivado FPGA design flow from RTL sources to bitstream. Use when asked to synthesize, implement, build, or compile an FPGA design. Also handles project creation, checkpoint management, and run orchestration.
Analyze and fix clock domain crossing violations. Use when CDC violations appear, when auditing multi-clock designs, or when reviewing set_false_path and set_max_delay exceptions for safety.
Author and audit Vivado XDC constraint files. Use when creating constraints, finding unconstrained paths, debugging timing exceptions, checking clock definitions, or auditing I/O delays for completeness.
Create Pblock floorplan constraints in Vivado. Use when dealing with placement congestion, SSI multi-die devices, reconfigurable partitions (DFX), or when critical paths need physical locality.
Run a complete Vivado design flow: project creation, synthesis, implementation, bitstream. Use when asked to build, synthesize, implement, or compile an FPGA design from RTL sources.
Run Vivado implementation phases: opt_design, place_design, phys_opt_design, route_design. Use when asked to run implementation, choose implementation directives, or re-run specific implementation phases.