菜单
Memory hierarchy skill for caches, coherence, and locality. Use when explaining cache levels, associativity, false sharing, prefetching, or MESI coherence. Activates on queries about cache hierarchy, L1 L2 L3, false sharing, cache line, prefetch, or cache coherence.
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基于 SOC 职业分类
| name | memory-hierarchy-and-caches |
| description | Memory hierarchy skill for caches, coherence, and locality. Use when explaining cache levels, associativity, false sharing, prefetching, or MESI coherence. Activates on queries about cache hierarchy, L1 L2 L3, false sharing, cache line, prefetch, or cache coherence. |
Teach CPU memory hierarchy: cache levels, associativity, line size, coherence protocols, false sharing, and prefetch behavior — architectural depth complementing optimization practice in skills/low-level-programming/cpu-cache-opt.
Registers
├── L1d / L1i (per core, ~32 KiB, ~4 cycles)
├── L2 (per core, ~256 KiB – 1 MiB)
├── L3 (shared last-level, MiB – tens of MiB)
├── DRAM (hundreds of cycles)
└── Storage / NUMA remote (much slower)
Embedded MCUs may have only tightly-coupled memory (no L2/L3).
getconf LEVEL1_DCACHE_LINESIZE)/* Bad — two atomics on same cache line */
struct {
atomic_int counter_a;
atomic_int counter_b;
} stats;
/* Good — pad to cache line */
struct alignas(64) {
atomic_int counter_a;
char pad[64 - sizeof(atomic_int)];
atomic_int counter_b;
} stats;
MESI states: Modified, Exclusive, Shared, Invalid. Writes invalidate other cores' copies of the line — why atomics and locks ping cache lines.
#ifdef __builtin_prefetch
for (int i = 0; i < n; i++) {
__builtin_prefetch(&data[i + 8], 0, 3);
process(data[i]);
}
#endif
Hardware stride prefetchers detect sequential access; random access misses.
perf stat -e cache-references,cache-misses,L1-dcache-load-misses ./app
/memory-hierarchy-and-caches Diagnose false sharing in this per-thread stats array
| Symptom | Cause | Fix |
|---|---|---|
| Scaling collapses | False sharing | Line-align per-thread data |
| High LLC misses | Working set > cache | Block algorithms; NUMA pin |
| DMA incoherence | CPU cache vs device | Flush/invalidate on MCU; dma_sync on Linux |
| Prefetch hurt | irregular access | Remove manual prefetch |
| Huge struct copies | AoS cold lines | SoA layout — see cpu-cache-opt |
skills/low-level-programming/cpu-cache-opt — practical optimizationskills/computer-architecture/cpu-pipelines-and-hazards — load-use stallsskills/computer-architecture/virtual-memory-paging-and-tlb — TLB missesskills/allocators/numa-programming — remote memory latencyskills/profilers/hardware-counters — perf counter eventsCustom allocator skill for memory allocation strategies. Use when implementing pool/slab/arena allocators, tuning jemalloc/mimalloc, writing Rust GlobalAlloc, or benchmarking allocator performance. Activates on queries about jemalloc, mimalloc, tcmalloc, arena allocator, GlobalAlloc, or fragmentation.
NUMA programming skill for multi-socket memory locality. Use when detecting NUMA topology, binding processes with numactl, using libnuma API, building NUMA-aware data structures, or measuring remote access penalties. Activates on queries about numactl, libnuma, NUMA topology, mbind, lstopo, or remote memory access.
AF_XDP skill for high-performance XDP sockets. Use when creating AF_XDP sockets, configuring UMEM and XSK rings, XDP_REDIRECT programs, copy vs zero-copy mode, or comparing with DPDK. Activates on queries about AF_XDP, xsk_umem, XDP_REDIRECT, libbpf xsk, or zero-copy XDP.
DPDK skill for userspace packet I/O. Use when initializing EAL, configuring PMD drivers, using mbuf pools and rte_ring, setting up huge pages, RSS, or testpmd validation. Activates on queries about DPDK, EAL, rte_eth_rx_burst, hugepages, PMD, or testpmd.
io_uring skill for Linux async I/O. Use when building high-performance servers with liburing, multi-shot operations, provided buffers, fixed files, zero-copy send, or tokio-uring. Activates on queries about io_uring, SQE/CQE, liburing, IORING_OP_PROVIDE_BUFFERS, or io_uring vs epoll.
Bare-metal ADC and DAC skill. Use when configuring analog sampling, DMA-driven ADC, calibration, or DAC output on MCUs. Activates on queries about ADC bare-metal, sampling time, DMA ADC, or DAC channel setup.