FPGA-Agent

Vitis HLS synthesis assistant for C/C++ to RTL conversion. Covers kernel development, pragma optimization, interface configuration, and synthesis report analysis. For post-synthesis implementation use vivado-impl, for timing analysis use vivado-analysis, for hardware debug use vivado-debug.

Use this skill when the user needs help with Vivado design analysis, timing report interpretation, or timing closure. This includes report_timing interpretation (slack calculation, path analysis, clock skew/uncertainty), report_timing_summary signoff verification, report_qor_assessment (QoR scoring 1-5, assessment categories), report_qor_suggestions (automated optimization suggestions, .rqs workflow), report_design_analysis (timing path characteristics, complexity/Rent analysis, congestion analysis), report_methodology (design rule compliance), report_utilization (resource usage analysis), report_cdc (clock domain crossing checks), report_drc (design rule checks), report_bus_skew, timing closure strategies (setup/hold violation resolution, congestion mitigation), message severity management, and design check waivers. This skill provides analysis and interpretation knowledge — for TCL command execution use vivado-tcl, for constraint modifications use vivado-constraints, for implementation strategy changes use

Use this skill when the user needs help writing XDC/SDC timing or physical constraints for Vivado FPGA designs. This includes clock definitions (create_clock, create_generated_clock, virtual clocks), I/O delay constraints (set_input_delay, set_output_delay, DDR timing), timing exceptions (set_false_path, set_multicycle_path, set_max_delay, set_min_delay), clock domain crossing (CDC) constraints (set_clock_groups, set_bus_skew), clock uncertainty/jitter/latency, physical constraints (IOSTANDARD, PACKAGE_PIN, LOC, Pblock, placement, routing), XDC precedence rules, constraint scoping (SCOPED_TO_REF), constraint ordering optimization, or constraint debugging (check_timing, report_exceptions, report_clock_interaction). Trigger when the user mentions XDC, SDC, timing constraints, clock constraints, IO delay, false path, multicycle path, clock groups, or physical pin assignment. For timing report interpretation and analysis use vivado-analysis.

Use this skill when the user needs help with Vivado in-system debugging, hardware programming, or debug core configuration. This includes ILA (Integrated Logic Analyzer) configuration and trigger strategies, VIO (Virtual I/O) usage for signal monitoring and control, JTAG-to-AXI Master for AXI transaction generation, mark_debug attribute and debug probing flows (Netlist Insertion, HDL Instantiation), Set Up Debug Wizard, ILA cross-trigger architecture, debug core timing impact and mitigation, Vivado Hardware Manager operation, FPGA/SoC device programming, Versal debugging architecture (AXI4 Debug Hub, CIPS integration), SVF file programming, debug clock requirements, and common debug error troubleshooting. This skill provides debugging strategy and decision-making knowledge — for TCL command execution use vivado-tcl, for implementation strategies use vivado-impl, for timing analysis use vivado-analysis.

Use this skill when the user needs help with Vivado implementation strategy selection and optimization. This includes opt_design (logic optimization directives and options), place_design (placement directives, congestion analysis, PSIP physical synthesis), phys_opt_design (physical optimization - fanout/placement/routing/SLR crossing/register optimization, hold fixing), route_design (routing directives, congestion resolution, pre-routing critical nets), power_opt_design (clock gating, BRAM power optimization), incremental implementation (read_checkpoint -incremental, auto_incremental, reuse analysis), ECO flow, implementation run strategies (Performance/Congestion/Area strategies), or any question about choosing between implementation directives or resolving timing/congestion issues during implementation. This skill provides decision-making knowledge for the implementation phase — for TCL command execution use vivado-tcl, for synthesis use vivado-synth, for constraints use vivado-constraints, for timing repor

Use this skill when the user needs help with Vivado simulation strategy, flow selection, and debugging. This includes behavioral simulation (RTL functional verification), post-synthesis simulation (netlist functional verification), post-implementation timing simulation (SDF back-annotation, timing verification), Vivado Simulator xsim usage (xvlog/xvhdl/xelab/xsim three-step flow, launch_simulation Project Mode), third-party simulator integration (Questa/ModelSim/VCS/Xcelium/Riviera/ActiveHDL, compile_simlib, export_simulation), SAIF/VCD power simulation (open_saif/log_saif, open_vcd/log_vcd, read_saif + report_power), simulation netlist generation (write_verilog -mode funcsim/timesim, write_sdf), xsim debugging commands (add_force, add_wave, log_wave, add_bp, step, run, restart, get_objects, get_value), simulation properties and settings, glbl.v usage, or any question about choosing the right simulation approach for verification or power analysis.

Use this skill when the user needs help with Vivado synthesis strategy selection, synthesis attribute configuration, synth_design option tuning, resource inference control (RAM/DSP/SRL/BRAM), hierarchy optimization (flatten_hierarchy, KEEP_HIERARCHY), OOC (out-of-context) synthesis, incremental synthesis, RTL linting, Block-Level synthesis (BLOCK_SYNTH), or any synthesis optimization decision. Trigger when the user mentions synthesis strategies, synthesis directives, synthesis attributes, resource mapping control, FSM encoding, retiming, or asks how to optimize synthesis results for area/timing/power. This skill provides decision-making knowledge — for TCL command execution, use vivado-tcl skill.

Use this skill when the user wants to generate, write, or execute Vivado/Vitis TCL scripts for FPGA design flows. This includes creating projects, running synthesis/implementation, programming devices, working with IP Integrator block designs, debug core insertion, constraint management, simulation, and any Vivado automation task. Trigger when the user mentions Vivado, Vitis, FPGA, TCL scripts for hardware design, bitstream generation, XDC constraints, ILA/VIO debug, or any Xilinx/AMD FPGA toolchain task. This skill generates and executes TCL — it does NOT analyze Vivado output or reports. For debug strategy and core configuration decisions use vivado-debug, for timing analysis use vivado-analysis.