菜单
Generate Synopsys .db technology or stub libraries for early synthesis and link. Use when converting Liberty .lib to .db with lc_shell, or when creating a minimal black-box Liberty/.db from a Verilog top module port list.
用 Codex 或 Claude 帮你安装 复制这段 Prompt，粘贴到 Codex、Claude 或其他助手里，让它检查 Skill 页面并帮你完成安装。
Create and operate canonical SoC project/module scaffolds through registered MCP tools for filelists, lint, compile, simulation, regression, coverage, and synthesis. Use for SoC project setup and any EDA Make-target execution.
Close stale multi-stage SoC delivery evidence for a router-selected merge or signoff packet. Use only when vibe-soc-loop delegates final architecture, doc, RTL, verification, synthesis, integration, or PD closure; do not use for ordinary dev iterations.
Route one-sentence vibe_soc feature, RTL, integration, verification, synthesis, register, CRG, low-power, or PD requests into the smallest safe Loop execution packet. Use for SoC work that needs task classification, MCP selection, pipeline state, or delivery closure.
Prepare and run local-default OpenROAD-flow-scripts physical-design handoff for silicon-crew SoC projects. Use when Codex needs to generate ORFS config/SDC under pd/openroad, run synth/floorplan/place/cts/route/finish/all stages through the default local ORFS path or explicit container backends, summarize OpenROAD reports/results, or connect vibe_soc-style RTL projects to OpenROAD.
Convert reviewed clock/reset Excel design tables into Draw.io and Excalidraw topology diagrams. Use for CRG source, mux, divider, OCC, ICG, and reset-chain visualization.
Convert a CRG requirement table into clock/reset design tables, PLL recommendations, and an architecture report. Use before clock/reset diagram generation when requirements are supplied as Excel or CSV.
基于 SOC 职业分类
| name | lib-db-gen |
| description | Generate Synopsys .db technology or stub libraries for early synthesis and link. Use when converting Liberty .lib to .db with lc_shell, or when creating a minimal black-box Liberty/.db from a Verilog top module port list. |
Use this skill when a flow needs a Synopsys .db and only has either a Liberty .lib or an RTL top module whose ports should become a black-box stub cell.
The bundled script is scripts/lib_db_gen.py.
Convert an existing Liberty file to DB:
python3 .agents/skills/lib-db-gen/scripts/lib_db_gen.py convert \
--lib path/to/input.lib \
--db path/to/output.db
Generate an early black-box Liberty from a Verilog top and compile it to DB:
python3 .agents/skills/lib-db-gen/scripts/lib_db_gen.py stub \
--top-v path/to/top.v \
--top top_module_name \
--lib path/to/top_stub.lib \
--db path/to/top_stub.db
Use --no-run to only emit the .lib and the Library Compiler Tcl script. Use --lc-shell /path/to/lc_shell when lc_shell is not on PATH. Use --work-dir <dir> to control Library Compiler's command file, lc_command.log, and lc_output.txt; by default this is <db-output-dir>/lc_work, not the repository root.
The generated <db-stem>.lc.tcl is temporary by default: remove it only after lc_shell produces a non-empty current-run .db that is atomically installed at the requested output path, and retain it when conversion fails or --no-run is selected. Use --keep-tcl to preserve a reusable final-output command file after a successful conversion. Use --tcl <path> only to override its location; cleanup semantics remain unchanged. Reject resolved-path collisions among Tcl, DB, Liberty, and Verilog inputs before writing any file.
convert for real Liberty to .db conversion.stub only for early integration, link, or black-box bring-up. The generated cell has ports and zero-area placeholder attributes; it is not timing or power evidence..db, .lib, and LC logs out of Git unless they are reviewed release collateral.scripts/local.mk at the generated .db, for example SKY130HD_DC_DB := /path/to/lib.db.stub parses ANSI-style module headers and simple non-ANSI declarations.[7:0] become Liberty bus types. Parameterized widths are treated as scalar with a warning; use a resolved wrapper if bus width fidelity matters.