circuit-designer

name

circuit-designer

description

Generate, review, and verify electronic circuits using a structured Circuit DSL with outputs for SVG schematics, SPICE simulation netlists, KiCad schematic/PCB scaffolds, ERC/DRC automation, PCB constraints, and staged design workflows. Use when Codex is asked to design circuits, draw schematics, create SVG circuit diagrams, generate KiCad projects, simulate analog circuits, plan PCB layouts, or build complex boards such as Linux carrier boards.

Circuit Designer

Operating Model

Use a staged workflow. Do not jump from natural language directly to KiCad or PCB for nontrivial designs.

1. Capture requirements: function, supply rails, IO, environment, accuracy, safety, cost, package constraints, and required outputs.
2. Draft a Circuit DSL document before producing artifacts. Use JSON when no YAML parser is available.
3. Validate the DSL with scripts/validate_dsl.py.
4. Complete common missing parts and motifs with scripts/complete_circuit.py when the DSL is partial.
5. Generate only the requested outputs:
   • Schemdraw SVG schematic for supported analog motifs: scripts/render_schemdraw_svg.py
   • Intent-driven SVG schematic fallback: scripts/render_intent_svg.py
   • Layout-aware SVG schematic fallback: scripts/render_schematic_svg.py
   • Net overview SVG fallback: scripts/render_svg.py
   • SPICE netlist: scripts/emit_spice.py
   • ngspice run: scripts/run_ngspice.py
   • KiCad schematic scaffold: scripts/emit_kicad_sch.py
   • KiCad PCB scaffold: scripts/emit_kicad_pcb.py
   • KiCad ERC/DRC wrappers: scripts/run_kicad_checks.py
6. Review generated artifacts against the requirements and fix the DSL, not the generated outputs, unless the user explicitly asks for hand edits.

Treat the DSL as the source of truth. Generated files may be overwritten.

Design Safety Rules

Require explicit review gates for mains voltage, batteries above common SELV limits, medical/safety equipment, high-current power, RF, DDR memory, PCIe, USB 3+, HDMI, Ethernet PHY layout, switch-mode power supplies, and Linux/SoC boards.

For complex boards, prefer vendor reference designs and modules/SOMs. Never invent pinouts, package data, impedance rules, DDR topology, or power sequencing from memory. Ask for datasheets/reference designs or use only clearly supplied data.

DSL First

Read references/dsl-schema.md before creating or modifying a DSL document. For reusable design patterns, load only the relevant reference:

• references/analog-patterns.md for filters, oscillators, op-amp circuits, and SPICE checks.
• references/power-design.md for regulators, rails, protection, decoupling, and power-tree reviews.
• references/digital-interfaces.md for MCU, Linux/SOM carrier, USB, Ethernet, clocks, reset, and boot straps.
• references/pcb-layout-rules.md for placement, netclasses, routing constraints, and DRC strategy.
• references/kicad-generation.md for KiCad output workflow and limitations.
• references/simulation-tests.md for choosing analyses and pass/fail checks.
• references/completion-rules.md for automatic circuit completion behavior.
• references/examples.md for compact examples.

If a requested circuit or schematic pattern is not covered by the current DSL, motif library, renderer, checker, or examples, extend the library first. Add the smallest reusable capability that fits the request, then express the design through that capability instead of bypassing the staged workflow with one-off generated output.

Output Policy

For simple analog circuits, produce SVG and SPICE first, then KiCad if requested.

For KiCad work, generate a scaffold that is easy to inspect and finish in KiCad. Run KiCad CLI checks when KiCad is installed. If KiCad is unavailable, state that the scaffold was generated but not ERC/DRC checked.

For PCB work, generate constraints and an initial board scaffold before attempting autorouting. Use autorouting as a draft only; do not represent it as production-ready without DRC and human layout review.

Script Usage

All scripts accept --help.

python scripts/validate_dsl.py design.json
python scripts/complete_circuit.py design.json --out build/design.completed.json
python scripts/circuit_pipeline.py design.json --out-dir build
python scripts/render_schemdraw_svg.py design.json --out build/schematic.svg
python scripts/render_intent_svg.py design.json --out build/intent_schematic.svg
python scripts/render_schematic_svg.py design.json --out build/layout_schematic.svg
python scripts/adjust_schematic_layout.py design.json --out build/design.adjusted.json
python scripts/render_svg.py design.json --out build/net_overview.svg
python scripts/emit_spice.py design.json --out build/circuit.cir
python scripts/run_ngspice.py build/circuit.cir --out-dir build/sim
python scripts/emit_kicad_sch.py design.json --out-dir build/kicad
python scripts/emit_kicad_pcb.py design.json --out-dir build/kicad
python scripts/run_kicad_checks.py build/kicad/project.kicad_pro

If a script reports a structural problem, fix the DSL and rerun downstream generation.

Prefer schematic_intent over raw coordinate-based schematic for analog circuits. Raw coordinates are a fallback, not the desired source of truth.

The Schemdraw renderer is motif-driven, not a flat-netlist autolayout engine. Add new analog coverage by adding reusable motifs in scripts/schematic_motifs.py and expressing the circuit in schematic_intent.motifs.