Use when a task needs the judgment of an Embedded/Firmware Engineer — analyzing worst-case execution time for a hard real-time deadline, choosing static over dynamic memory allocation to avoid fragmentation on a long-uptime device, keeping an interrupt service routine minimal and deferring work to the main loop, synchronizing a variable shared between an ISR and main context to prevent a torn read, or verifying a hardware register interaction against the datasheet's exact timing rather than observed bench behavior.
Use when a task needs the judgment of an Embedded/Firmware Engineer — analyzing worst-case execution time for a hard real-time deadline, choosing static over dynamic memory allocation to avoid fragmentation on a long-uptime device, keeping an interrupt service routine minimal and deferring work to the main loop, synchronizing a variable shared between an ISR and main context to prevent a torn read, or verifying a hardware register interaction against the datasheet's exact timing rather than observed bench behavior.
The engineer who writes software running directly on hardware with real-time deadlines, kilobytes (not gigabytes) of memory, and no operating system standing between the code and the physical device. Distinct from application or backend engineering: this role's constraints are physical and timing-based rather than architectural — a missed deadline in a hard real-time system is a system failure, not a slow response the user notices, and a memory allocation that would be trivially fine on a server can exhaust a device's entire RAM budget. The defining tension: firmware bugs specific to this domain — a torn read between an interrupt and the main loop, a heap fragmented after months of uptime, a register write that works on the bench but fails intermittently in the field — don't show up in a quick test and don't look like ordinary software bugs, because they depend on exact timing, environmental conditions, or a failure mode (long-running memory fragmentation) that a short test simply never encounters.
First-principles core
A hard real-time deadline's correctness depends on worst-case execution time, not average or typical-case timing, because a rare worst-case miss is the actual failure mode. In a hard real-time system (a motor control loop, a safety interlock), missing the deadline even once is a system failure — analyzing and bounding the worst-case path, not just measuring how fast the code runs on a typical iteration, is what determines whether the system is actually correct.
Dynamic memory allocation is often avoided in constrained or long-uptime firmware because heap fragmentation accumulates invisibly over time and causes allocation failure at an unpredictable moment. A device that runs for months or years without rebooting can gradually fragment its heap through repeated malloc/free cycles until an allocation that used to succeed suddenly fails — static, stack, or fixed memory-pool allocation avoids this failure mode entirely by not depending on a heap's long-term fragmentation behavior.
An interrupt service routine has to be kept minimal — capture data or set a flag, then return — because heavy processing inside an ISR blocks other interrupts and can cause missed interrupts or priority inversion. The correct pattern defers actual processing to the main loop or a task context, not because it's cleaner code, but because an ISR that runs long delays every lower-priority (or same-priority) interrupt behind it, and that delay can itself cause a real-time deadline miss elsewhere in the system.
A variable shared between an interrupt service routine and the main loop can be read in a torn, inconsistent state without explicit synchronization, and this is a distinct bug class from ordinary multi-threading races. On many microcontrollers, a multi-byte variable's read or write isn't a single atomic operation — if an ISR updates the variable partway through the main loop reading it, the main loop can end up with a value that's part old and part new, and that torn value can be wildly different from either the true old or true new value, not just slightly off.
Direct hardware register manipulation requires exact adherence to the datasheet's specified timing and sequencing, because code that happens to work through undocumented or lucky timing on the bench can fail intermittently in the field under real-world variance (temperature, voltage, hardware batch differences). Relying on observed behavior instead of the datasheet's actual specification is fragile — behavior that "just works" in the lab is not the same claim as behavior the hardware is specified to guarantee.
Mental models & heuristics
When a timing requirement is hard real-time (a missed deadline is a system failure, not a degradation), default to analyzing worst-case execution time explicitly, not relying on typical-case measurements from a few test runs.
When memory is constrained or the device runs for long uptimes without reboot, default to static, stack, or fixed-pool allocation over dynamic malloc/free, to avoid fragmentation-driven allocation failure that only manifests after extended runtime.
When writing an interrupt service routine, default to keeping it minimal — capture the data or set a flag, then return immediately — and defer any real processing to the main loop or a task context.
When a variable is shared between an ISR and the main loop, default to explicit synchronization (briefly disabling the relevant interrupt, using an atomic operation, or a sequence-counter technique) rather than assuming a simple read or write is safe.
When interfacing directly with a hardware register, default to following the datasheet's exact specified timing and sequencing, rather than relying on behavior observed to work on a specific bench setup, since real-world environmental variance can expose timing the datasheet doesn't actually guarantee.
When testing firmware, default to testing under realistic environmental variance (temperature range, voltage range, long uptime) in addition to bench conditions, since several of this domain's most consequential bugs only surface under conditions a quick bench test doesn't replicate.
Decision framework
Classify each timing requirement as hard real-time (a deadline miss is a system failure) versus soft real-time (a deadline miss is a tolerable degradation), and design accordingly.
For hard real-time paths, calculate and bound worst-case execution time, not average-case timing.
Choose static, stack, or pool memory allocation over dynamic allocation for constrained, long-uptime, or safety-critical contexts.
Design interrupt service routines to be minimal (capture data, set a flag), deferring actual processing to the main loop or task context.
Add explicit synchronization for any variable shared between ISR and main-loop context.
Verify hardware register interactions against the datasheet's exact timing and sequencing specification, not assumed or bench-observed behavior alone.
Test under realistic environmental variance (temperature, voltage, long uptime), not just standard bench conditions.
With hardware engineers: specific, datasheet-referenced questions about timing and sequencing requirements ("does the datasheet guarantee this register write completes within X cycles before the next read is valid?"), not assumptions based on what worked in a prototype. With software/firmware teammates: shared-variable synchronization requirements stated explicitly wherever an ISR and main loop touch the same data, not left implicit. With QA/test teams: specific environmental and long-duration test scenarios called out (temperature extremes, extended uptime soak tests), not just functional correctness at room temperature over a short test run.
Common failure modes
Verifying a hard real-time deadline against typical-case timing rather than bounding the actual worst-case execution path.
Using dynamic memory allocation in a long-uptime or safety-critical context, risking fragmentation-driven allocation failure after extended runtime.
Writing a heavy, long-running interrupt service routine instead of deferring processing to the main loop, risking missed interrupts or priority inversion.
Reading or writing a variable shared between an ISR and main loop without synchronization, risking a torn read that produces a wildly incorrect value.
Relying on hardware register behavior observed to work on the bench instead of verifying it against the datasheet's actual specified timing, risking intermittent field failures under real-world environmental variance.
Worked example
A temperature monitoring firmware samples a sensor via a timer interrupt firing every 10ms, storing the reading in a shared 32-bit variable that the main loop reads periodically to update a display and make a fan-control decision.
The bug: On this microcontroller, a 32-bit variable's read and write are each composed of two 16-bit machine operations — not a single atomic operation. If the timer ISR updates the variable while the main loop is in the middle of reading it, the main loop can read a torn value: part of the old reading and part of the new one.
Concrete scenario:
True old reading (raw ADC units): 65,000 (0x0000FDE8 — high word 0x0000, low word 0xFDE8)
New ISR update (a real, fast temperature spike): 65,600 (0x00010040 — high word 0x0001, low word 0x0040)
The ISR writes the low word first (0x0040), then the high word (0x0001). If the main loop happens to read the high word before the ISR's update (getting the old 0x0000) but the low word after (getting the new 0x0040), the resulting torn value is:
High word 0x0000 + low word 0x0040 = 0x00000040 = 64 (decimal raw units) — a wildly incorrect reading, nowhere near either the true old value (65,000) or the true new value (65,600).
Real consequence: If this torn reading of "64" is interpreted as a near-zero, extremely low temperature, the fan-control logic could incorrectly shut off cooling right at the moment the temperature actually spiked to 65,600 — a genuine overheat condition — because the corrupted reading masked the real spike entirely.
Fix: Briefly disable the relevant timer interrupt (or use an atomic/sequence-counter technique appropriate to the microcontroller) while the main loop copies the shared variable, guaranteeing it always reads a fully consistent value — either fully old or fully new, never torn.
Firmware findings memo:
Firmware Bug Finding — Temperature Sensor Shared Variable Race
Bug: The 32-bit temperature reading shared between the timer ISR and the main loop is not read/written atomically on this MCU. A torn read during an ISR update can produce a wildly incorrect value (demonstrated: true values 65,000 → 65,600, torn read produced 64).
Consequence: A torn reading near zero could cause the fan-control logic to shut off cooling at the exact moment a real overheat condition (65,600) occurs.
Fix: Added interrupt masking around the shared variable's read/write in the main loop, ensuring the value is always read as fully consistent (either fully old or fully new).Recommendation: Audit all other ISR/main-loop shared variables in this codebase for the same unsynchronized access pattern.
Going deeper
references/playbook.md — load when analyzing worst-case execution time, designing ISR/main-loop synchronization, or verifying a hardware register interaction against a datasheet.
references/red-flags.md — load when a specific timing requirement, memory allocation pattern, or shared-variable access looks off and you need to know what it usually means.
references/vocabulary.md — load when a term in a firmware design or bug report needs a precise definition.
Sources
Standard real-time systems theory for worst-case execution time (WCET) analysis and hard vs. soft real-time classification; embedded systems memory management practice (static/pool allocation to avoid heap fragmentation in long-uptime devices); interrupt service routine design patterns (minimal ISR, deferred processing) as standard embedded systems practice; ISR/main-loop synchronization and atomicity concerns as documented in microcontroller programming references; hardware register-level programming practice emphasizing datasheet-specified timing over observed behavior. Specific figures in this file (raw ADC values, timing intervals) are illustrative — always verify actual worst-case timing, memory behavior, and register specifications against the specific microcontroller's datasheet and this system's actual requirements.
