菜单
Use when planning RTL module structure from microarchitecture docs. Triggers on '模块结构', '端口列表', '子模块划分', '文件清单', 'module structure', 'port list'. Extracts ports, submodule partitioning and file list from microarch docs.
用 Codex 或 Claude 帮你安装 复制这段 Prompt，粘贴到 Codex、Claude 或其他助手里，让它检查 Skill 页面并帮你完成安装。
基于 SOC 职业分类
Autonomous iterative research loop. Takes a topic, runs web searches, fetches sources, synthesizes findings, and files everything into the wiki as structured pages. Based on Karpathy's autoresearch pattern: program.md configures objectives and constraints, the loop runs until depth is reached, output goes directly into the knowledge base. Triggers on: "/autoresearch", "autoresearch", "research [topic]", "deep dive into [topic]", "investigate [topic]", "find everything about [topic]", "research and file", "go research", "build a wiki on".
Visual layer of the wiki. Add images, text cards, PDFs, and wiki pages to Obsidian canvas files with auto-positioning inside zones. Integrates with /banana for image capture. Triggers on: /canvas, canvas new, canvas add image, canvas add text, canvas add pdf, canvas add note, canvas zone, canvas list, canvas from banana, add to canvas, put this on the canvas, open canvas, create canvas.
Use when running RTL lint checks. Triggers on 'lint', 'verilator', 'verible', 'spyglass', '语法检查', '可综合性', '组合环路', 'latch检查', 'rtl lint', 'lint检查'. Supports multiple EDA tools with auto-detection.
Use when processing vc-spyglass lint log output to resolve violations. Maps lint rules to JMTAG execution levels, proposes RTL fixes or generates waive files. Triggered by keywords like spyglass, lint log, lint violation, JMTAG, waive file, lint rules.
Use when generating comprehensive SDC timing constraints from FS/microarch documents. Triggers on '生成SDC', 'SDC约束', 'timing constraints', '时序约束文件', 'write SDC', 'SDC文件'. Produces production-quality SDC covering clocks, I/O, design rules, timing exceptions, and area/power constraints.
Use when running SpyGlass CDC checks on RTL. Triggers on 'cdc检查', 'cdc check', 'spyglass cdc', '跨时钟域检查', 'cdc验证', 'clock domain crossing', 'cdc setup', 'cdc_verify'. Generates SGDC constraints, runs CDC goals, produces violation reports.
| name | chip-impl-module-structure |
| description | Use when planning RTL module structure from microarchitecture docs. Triggers on '模块结构', '端口列表', '子模块划分', '文件清单', 'module structure', 'port list'. Extracts ports, submodule partitioning and file list from microarch docs. |
从微架构文档提取结构信息，规划 RTL 实现所需的端口、子模块、文件清单。
microarch_doc: 微架构文档路径cbb_docs: CBB 文档（来自 RAG 检索）Glob 搜索 {module}_work/ds/doc/ua/*.md 获取微架构文档列表。若文件不存在，暂停并提示用户.v / _sva.sv / _intf.sv / .sdc / _tb.v{module}_work/port_list: 端口列表（信号名/方向/位宽/类型）submodule_list: 子模块列表（模块名/功能/依赖）file_list: 文件清单work_dir: 工作目录路径{module}_work/
├── rtl/ — RTL 源码
├── syn/ — SDC + Makefile
├── ds/
│ ├── doc/ — CBB 清单
│ ├── run/ — 运行脚本
│ └── report/ — Lint/综合报告
端口列表必须与微架构 §4.1 完全一致。
本 Skill 不涉及架构决策，仅从微架构提取结构信息。
执行完成后记录到 {work_dir}/ds/report/metrics/module_structure.json：
{"stage_id": "module_structure", "duration_ms": 0, "iteration_count": 1}
示例 1：
示例 2：
port_list、submodule_list、file_list| 场景 | 触发条件 | 处理动作 |
|---|---|---|
| 微架构端口列表缺失 | §4.1 无端口表格 | 暂停，提示用户补充微架构端口定义 |
| 子模块定义不完整 | §5 无子模块实例化列表 | 暂停，提示用户补充子模块设计 |
| 工作目录创建失败 | 路径权限或磁盘问题 | 提示用户检查路径权限 |
| 端口与微架构不一致 | 提取结果与 §4.1 矛盾 | 以微架构为准，标注差异项 |
检查前：
检查后：
port_list 与微架构 §4.1 完全一致submodule_list 包含所有子模块{module}_work/ 已创建且结构正确{work_dir}/ds/report/metrics/module_structure.json