zhaixin244-wq/fnw - 第 2 页

chip-png-wavedrom-gen

Use when generating Wavedrom timing diagrams as PNG images. Triggers on '时序图', 'wavedrom', 'timing diagram', '波形图', '时序分析图', 'generate wavedrom'. Compiles Wavedrom JSON to PNG using wavedrom-cli.

chip-ppa-formatter

Use when formatting PPA specification tables. Triggers on 'PPA表', 'PPA格式', 'ppa formatter', '面积表', '功耗表', '性能表', 'PPA规格'. Outputs structured PPA specs with unit normalization and constraint expressions.

chip-protocol-compliance-checker

Use when checking module interface protocol compliance. Triggers on '协议检查', 'protocol check', 'AXI合规', 'APB合规', '协议合规', '接口规范', 'compliance'. Checks module interfaces against AXI/CHI/TileLink/APB protocol specifications.

chip-reliability-architect

Use when assessing reliability risks and designing mitigation. Triggers on '可靠性', 'SEU', '老化', 'IR Drop', 'EM', '热设计', 'reliability', 'ECC', 'TMR'. Evaluates SEU/aging/IR Drop/EM/thermal risks and proposes mitigation strategies.

chip-review-checklister

Use when reviewing FS, UA, or RTL documents against quality checklists. Triggers on 'review', '评审', '检查清单', 'checklist', 'review report', '评审报告', '自检报告'. Generates structured review checklist and report.

chip-rtl-bug-checker

Use when checking RTL code for common bugs and design issues. Triggers on 'bug', 'rtl bug', '检查rtl', 'rtl检查', 'bug check', 'rtl review', '代码检查', '设计缺陷'. Runs 6-category analysis: pipeline/FSM, input latch, interface, FIFO/flow, bitwidth, resource conflict.

chip-rtl-guideline-generator

Use when generating RTL coding guidelines from microarchitecture. Triggers on '编码规范', 'coding guideline', 'RTL指导', '实现指导', '可综合性', 'rtl guideline', '编码指南', 'coding guide'. Generates RTL coding standards and synthesizability implementation guidance from…

chip-synthesis-runner

Use when running Yosys synthesis on Verilog/RTL code. Triggers on '综合', 'synthesis', 'yosys', 'synth', '面积', 'timing', 'Fmax', '综合报告', '面积估计'. Runs Yosys and generates synthesis report with area and critical path info.

chip-traceability-linker

Use when building requirements traceability matrix (RTM). Triggers on 'RTM', '追溯矩阵', 'traceability', '需求追溯', '需求覆盖', '追溯矩阵'. Builds traceability from requirements to architecture, interface, PPA and verification.

chip-version-diff-generator

Use when comparing architecture document versions and generating change impact analysis. Triggers on '版本对比', 'version diff', '变更分析', '变更影响', '文档对比', 'change impact'. Compares two versions of architecture docs and outputs structured change impact analysis.

debate

Use when performing cross-model adversarial review of plans, architectures, or code. Triggers on 'debate', '辩论', '跨模型', '对手评审', 'adversarial review', '外部模型', 'cross-model'. Calls external LLM (Codex/Gemini/Kimi/GLM/MiMo/Claude) to challenge your plan with up…

原文语言：英语

deeptutor-research

通过 DeepTutor CLI 进行体系化知识研究。触发词：'DeepTutor 研究'、'深度研究'、'知识库检索'、'RAG 检索'、'deeptutor search'、'deeptutor research'。封装 kb create/add、deep_research、kb search、deep_solve、chat 等 CLI 调用，输出结构化 JSON。

deeptutor-setup

DeepTutor 部署检测与安装配置。触发词：'部署 DeepTutor'、'安装 DeepTutor'、'检查 DeepTutor'、'配置 DeepTutor'、'deeptutor setup'。检测 CLI 可用性、Python venv、依赖完整性、.env 配置，缺失时自动部署。

chip-arbiter-selector

Use when selecting arbitration strategy for RTL modules. Triggers on '仲裁', 'arbiter', 'round-robin', 'RR', 'WRR', '优先级', '公平性', '饥饿', 'arbiter selector'. Based on request pattern, channel count and QoS, selects Fixed Priority / Round-Robin / WRR and evaluates…

chip-cbb-decision

Use when deciding whether to abstract RTL logic as a reusable CBB module. Triggers on 'CBB', '复用', '抽象', '可复用模块', 'CBB决策', 'reuse', 'abstraction'. Evaluates interface standardization, parameterization, self-containment and reuse value.

chip-create-dir

Use when initializing chip module workspace directory structure. Triggers on '创建目录', '初始化目录', '目录结构', 'workspace', '工作目录', 'create dir'. Creates ds (design) and dv (verification) directory trees with standard subdirectories.

devils-advocate

Use when challenging decisions, plans, architecture, or code by arguing the opposing side. Triggers on 'devil', '对抗', '挑战', 'poke holes', 'what could go wrong', 'linus', 'ruthless', '暴露风险', '假设盲点', 'stress test'. Supports 4 intensity levels: gentle, balanced,…

原文语言：英语

claude-skill-verilog

Verilog/SystemVerilog coding style and Verilator workflow guidance

原文语言：英语

rag-query

Query the LLM Wiki knowledge base for protocol/CBB/architecture information

vf-pipeline

Use this skill to start or resume the VeriFlow RTL hardware design pipeline (architect to synth). Trigger this when the user asks to "run the RTL flow", "design hardware", or "start the pipeline". Pass the project directory path as the argument.

原文语言：英语

make-plan

Create a detailed, phased implementation plan with documentation discovery. Use when asked to plan a feature, task, or multi-step implementation — especially before executing with do.

原文语言：英语

mem-search

Search claude-mem's persistent cross-session memory database. Use when user asks "did we already solve this?", "how did we do X last time?", or needs work from previous sessions.

原文语言：英语

rag-project-query

Query the project-level LightRAG knowledge graph for project-specific context and decisions

原文语言：英语

rag-project-remember

Store project-specific knowledge into the project-level LightRAG knowledge graph

原文语言：英语

rag-project-sync

End-of-session review and sync of project-specific learnings to the project-level LightRAG graph

原文语言：英语

rag-remember

Store a fact, decision, or observation into the personal LightRAG knowledge graph immediately

原文语言：英语

rag-setup-project

Set up LightRAG persistent memory for a Cursor project with MCP configuration

原文语言：英语

rag-sync

End-of-session review and sync of learnings to the personal LightRAG knowledge graph

原文语言：英语

smart-explore

Token-optimized structural code search using tree-sitter AST parsing. Use instead of reading full files when you need to understand code structure, find functions, or explore a codebase efficiently.

原文语言：英语

timeline-report

Generate a "Journey Into [Project]" narrative report analyzing a project's entire development history from claude-mem's timeline. Use when asked for a timeline report, project history analysis, development journey, or full project report.

原文语言：英语

claude-code-plugin-release

Automated semantic versioning and release workflow for Claude Code plugins. Handles version increments across package.json, marketplace.json, and plugin.json, build verification, git tagging, GitHub releases, and changelog generation.

原文语言：英语