Arcadia-1/veriloga-skills

veriloga

Verilog-A language authoring guidance for writing, reviewing, or explaining .va behavioral modules. Use for Verilog-A syntax and semantics: modules and ports, disciplines and natures, analog blocks, branch access, contributions, events, parameters, arrays,…

لغة النص الأصلي: الإنجليزية

evas-sim

How to use the EVAS Verilog-A behavioral simulator (pip package: evas-sim). Use this skill whenever the user wants to simulate a Verilog-A (.va) model, run a Spectre (.scs) netlist, check simulation feasibility, install evas-sim, or read simulation output…

لغة النص الأصلي: الإنجليزية

openvaf

Compile Verilog-A device models with OpenVAF and simulate them in ngspice via OSDI. Use this skill whenever the user wants to: compile a .va file, run a Verilog-A model in ngspice, use OpenVAF, load an OSDI model, test a compact device model, or set up the…

لغة النص الأصلي: الإنجليزية