veriloga-skills

How to use the EVAS Verilog-A behavioral simulator (pip package: evas-sim). Use this skill whenever the user wants to simulate a Verilog-A (.va) model, run a Spectre (.scs) netlist, check simulation feasibility, install evas-sim, or read simulation output (tran.csv, strobe.txt). Trigger on phrases like "simulate this", "run this VA model", "can EVAS handle this", "evas run", "evas simulate", "check if this is simulatable", or any mention of evas-sim.

Write Verilog-A behavioral modules for analog/mixed-signal IC design (Cadence Virtuoso / Spectre). Covers 12 circuit categories. TRIGGER FIRST (before evas-sim) when the user needs to write or generate a new .va file. Key trigger phrases: "write", "create", "generate", "code", "implement" + "Verilog-A / veriloga / va / .va / behavioral model". Also triggers on: review/fix Verilog-A, "behavioral model", "veriloga", "analog HDL", circuit spec → behavioral model, "voltage-domain", "current-domain". Do NOT defer to evas-sim for authoring — evas-sim is for running an already-written file.

Compile Verilog-A device models with OpenVAF and simulate them in ngspice via OSDI. Use this skill whenever the user wants to: compile a .va file, run a Verilog-A model in ngspice, use OpenVAF, load an OSDI model, test a compact device model, or set up the OpenVAF + ngspice toolchain. Also use when the user mentions OSDI, compact models, BSIM, PSP, HICUM, or wants to simulate custom MOSFET/BJT/diode/varactor models written in Verilog-A. Complements the `veriloga` writing skill and the `ngspice` simulation skill.