القائمة
Run a complete Vivado design flow: project creation, synthesis, implementation, bitstream. Use when asked to build, synthesize, implement, or compile an FPGA design from RTL sources.
التثبيت باستخدام Codex أو Claude انسخ هذا Prompt والصقه في Codex أو Claude أو مساعد آخر ليراجع صفحة Skill ويثبّتها لك.
استنادا إلى تصنيف SOC المهني
Run a complete Vivado FPGA design flow from RTL sources to bitstream. Use when asked to synthesize, implement, build, or compile an FPGA design. Also handles project creation, checkpoint management, and run orchestration.
Analyze and fix clock domain crossing violations. Use when CDC violations appear, when auditing multi-clock designs, or when reviewing set_false_path and set_max_delay exceptions for safety.
Author and audit Vivado XDC constraint files. Use when creating constraints, finding unconstrained paths, debugging timing exceptions, checking clock definitions, or auditing I/O delays for completeness.
Insert ILA and VIO debug cores into a Vivado design. Use when asked to add hardware debug probes, set up ILA trigger conditions, insert VIO for stimulus injection, or generate .ltx probeinfo files.
Create Pblock floorplan constraints in Vivado. Use when dealing with placement congestion, SSI multi-die devices, reconfigurable partitions (DFX), or when critical paths need physical locality.
Run Vivado implementation phases: opt_design, place_design, phys_opt_design, route_design. Use when asked to run implementation, choose implementation directives, or re-run specific implementation phases.
| name | vivado-flow |
| description | Run a complete Vivado design flow: project creation, synthesis, implementation, bitstream. Use when asked to build, synthesize, implement, or compile an FPGA design from RTL sources. |
vivado is on PATH.create_project -in_memory -part <part_number>
read_verilog [glob src/*.v]
read_vhdl [glob src/*.vhd]
read_xdc constraints.xdc
set_property top <top_module> [current_fileset]
update_compile_order -fileset sources_1
synth_design -top <top_module> -part <part_number> -directive Default -flatten_hierarchy rebuilt -fsm_extraction auto -retiming
write_checkpoint -force /tmp/vivaclaw_post_synth.dcp
report_utilization -file /tmp/vivaclaw_rpt/post_synth_util.rpt
opt_design -directive Default
write_checkpoint -force /tmp/vivaclaw_post_opt.dcp
place_design -directive Default
write_checkpoint -force /tmp/vivaclaw_post_place.dcp
phys_opt_design -directive Default
route_design -directive Default
write_checkpoint -force /tmp/vivaclaw_post_route.dcp
vivado-timing.report_drc -file /tmp/vivaclaw_rpt/post_route_drc.rpt.write_bitstream if zero CRITICAL WARNINGS or ERRORS.write_bitstream -force /tmp/vivaclaw_output.bit