vivaclaw-agent

Run a complete Vivado FPGA design flow from RTL sources to bitstream. Use when asked to synthesize, implement, build, or compile an FPGA design. Also handles project creation, checkpoint management, and run orchestration.

Analyze and fix clock domain crossing violations. Use when CDC violations appear, when auditing multi-clock designs, or when reviewing set_false_path and set_max_delay exceptions for safety.

Author and audit Vivado XDC constraint files. Use when creating constraints, finding unconstrained paths, debugging timing exceptions, checking clock definitions, or auditing I/O delays for completeness.

Insert ILA and VIO debug cores into a Vivado design. Use when asked to add hardware debug probes, set up ILA trigger conditions, insert VIO for stimulus injection, or generate .ltx probeinfo files.

Create Pblock floorplan constraints in Vivado. Use when dealing with placement congestion, SSI multi-die devices, reconfigurable partitions (DFX), or when critical paths need physical locality.

Run a complete Vivado design flow: project creation, synthesis, implementation, bitstream. Use when asked to build, synthesize, implement, or compile an FPGA design from RTL sources.

Run Vivado implementation phases: opt_design, place_design, phys_opt_design, route_design. Use when asked to run implementation, choose implementation directives, or re-run specific implementation phases.

Create, configure, generate, and upgrade Xilinx IP cores. Use when instantiating IP catalog cores, configuring AXI interconnects, generating IP targets, handling OOC synthesis, upgrading stale IPs, or building block designs.

Analyze and reduce FPGA power consumption. Use when asked to measure power, run power optimization, reduce dynamic power, annotate switching activity, or audit clock and I/O power.

Parse Vivado reports and produce a structured design health score. Use when analyzing run results, comparing multiple runs, generating a health score, or surfacing key findings from report files.

Run Vivado simulations using xsim. Use when asked to simulate RTL, run behavioral, post-synthesis, or post-implementation simulation, or compile HDL for simulation.

Choose and run optimal synthesis strategy. Use when synthesizing a design, selecting synth directives, auditing BRAM/DSP/LUT inference quality, or improving synthesis QoR.

Analyze and fix timing violations. Use when WNS is negative, when asked to close timing, fix setup/hold violations, analyze critical paths, or improve max frequency.