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vivado-impl

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Run Vivado implementation phases: opt_design, place_design, phys_opt_design, route_design. Use when asked to run implementation, choose implementation directives, or re-run specific implementation phases.

التثبيت

التثبيت باستخدام Codex أو Claude انسخ هذا Prompt والصقه في Codex أو Claude أو مساعد آخر ليراجع صفحة Skill ويثبّتها لك.

تشغيل في Manus

المصدر

devansh0703

devansh0703/vivaclaw-agent

فتح مستودع GitHub عرض مستودعات المنشئ

تنزيل

تشغيل في Manus

المهن ذات الصلةSOC

استنادا إلى تصنيف SOC المهني

مطوّرو البرمجياتمهن الحاسوب والرياضيات·SOC 15-1252

SKILL.md

readonly

name	vivado-impl
description	Run Vivado implementation phases: opt_design, place_design, phys_opt_design, route_design. Use when asked to run implementation, choose implementation directives, or re-run specific implementation phases.

Vivado Implementation Runbook

1. Implementation Phases & Directives

Phase	Directives (Ascending Intensity)
opt	Default, Explore, ExploreWithRemap, AggressiveExplore
place	Default, WLDrivenPlacement, AltSpreadLogic_high, ExtraNetDelay_high
phys_opt	Default, Explore, AggressiveExplore, AlternativeFlowWithRetiming
route	Default, Explore, AggressiveExplore, MoreGlobalIterations

2. Implementation Execution

open_checkpoint /tmp/vivaclaw_post_synth.dcp
opt_design -directive <dir>
place_design -directive <dir>
phys_opt_design -directive <dir>
route_design -directive <dir>
write_checkpoint -force /tmp/vivaclaw_post_route.dcp

3. Partial Re-route (Fast Fix)

If only a few nets are failing:

route_design -unroute -nets [get_nets -hierarchical <pattern>]
route_design -directive AggressiveExplore -nets [get_nets -hierarchical <pattern>]

4. Incremental Flow

If a previous high-quality run exists:

read_checkpoint -incremental reference.dcp
place_design
route_design

Check get_property INCREMENTAL_REUSE [current_design] to verify reuse % (>90% ideal).

المزيد من هذا المستودع

نفس المستودع

vivado-flow

devansh0703/vivaclaw-agent

Run a complete Vivado FPGA design flow from RTL sources to bitstream. Use when asked to synthesize, implement, build, or compile an FPGA design. Also handles project creation, checkpoint management, and run orchestration.

2026-04-223

vivado-cdc

devansh0703/vivaclaw-agent

Analyze and fix clock domain crossing violations. Use when CDC violations appear, when auditing multi-clock designs, or when reviewing set_false_path and set_max_delay exceptions for safety.

2026-04-223

vivado-constraints

devansh0703/vivaclaw-agent

Author and audit Vivado XDC constraint files. Use when creating constraints, finding unconstrained paths, debugging timing exceptions, checking clock definitions, or auditing I/O delays for completeness.

2026-04-223

vivado-debug

devansh0703/vivaclaw-agent

Insert ILA and VIO debug cores into a Vivado design. Use when asked to add hardware debug probes, set up ILA trigger conditions, insert VIO for stimulus injection, or generate .ltx probeinfo files.

2026-04-223

vivado-floorplan

devansh0703/vivaclaw-agent

Create Pblock floorplan constraints in Vivado. Use when dealing with placement congestion, SSI multi-die devices, reconfigurable partitions (DFX), or when critical paths need physical locality.

2026-04-223

vivado-flow

devansh0703/vivaclaw-agent

Run a complete Vivado design flow: project creation, synthesis, implementation, bitstream. Use when asked to build, synthesize, implement, or compile an FPGA design from RTL sources.

2026-04-223

name	vivado-impl
description	Run Vivado implementation phases: opt_design, place_design, phys_opt_design, route_design. Use when asked to run implementation, choose implementation directives, or re-run specific implementation phases.

Vivado Implementation Runbook

1. Implementation Phases & Directives

Phase	Directives (Ascending Intensity)
opt	Default, Explore, ExploreWithRemap, AggressiveExplore
place	Default, WLDrivenPlacement, AltSpreadLogic_high, ExtraNetDelay_high
phys_opt	Default, Explore, AggressiveExplore, AlternativeFlowWithRetiming
route	Default, Explore, AggressiveExplore, MoreGlobalIterations

2. Implementation Execution

open_checkpoint /tmp/vivaclaw_post_synth.dcp
opt_design -directive <dir>
place_design -directive <dir>
phys_opt_design -directive <dir>
route_design -directive <dir>
write_checkpoint -force /tmp/vivaclaw_post_route.dcp

3. Partial Re-route (Fast Fix)

If only a few nets are failing:

route_design -unroute -nets [get_nets -hierarchical <pattern>]
route_design -directive AggressiveExplore -nets [get_nets -hierarchical <pattern>]

4. Incremental Flow

If a previous high-quality run exists:

read_checkpoint -incremental reference.dcp
place_design
route_design

Check get_property INCREMENTAL_REUSE [current_design] to verify reuse % (>90% ideal).