القائمة
Run Vivado simulations using xsim. Use when asked to simulate RTL, run behavioral, post-synthesis, or post-implementation simulation, or compile HDL for simulation.
التثبيت باستخدام Codex أو Claude انسخ هذا Prompt والصقه في Codex أو Claude أو مساعد آخر ليراجع صفحة Skill ويثبّتها لك.
استنادا إلى تصنيف SOC المهني
Run a complete Vivado FPGA design flow from RTL sources to bitstream. Use when asked to synthesize, implement, build, or compile an FPGA design. Also handles project creation, checkpoint management, and run orchestration.
Analyze and fix clock domain crossing violations. Use when CDC violations appear, when auditing multi-clock designs, or when reviewing set_false_path and set_max_delay exceptions for safety.
Author and audit Vivado XDC constraint files. Use when creating constraints, finding unconstrained paths, debugging timing exceptions, checking clock definitions, or auditing I/O delays for completeness.
Insert ILA and VIO debug cores into a Vivado design. Use when asked to add hardware debug probes, set up ILA trigger conditions, insert VIO for stimulus injection, or generate .ltx probeinfo files.
Create Pblock floorplan constraints in Vivado. Use when dealing with placement congestion, SSI multi-die devices, reconfigurable partitions (DFX), or when critical paths need physical locality.
Run a complete Vivado design flow: project creation, synthesis, implementation, bitstream. Use when asked to build, synthesize, implement, or compile an FPGA design from RTL sources.
| name | vivado-sim |
| version | 1.0.0 |
| description | Run Vivado simulations using xsim. Use when asked to simulate RTL, run behavioral, post-synthesis, or post-implementation simulation, or compile HDL for simulation. |
| metadata | {"openclaw":{"requires":{"bins":["vivado"]},"emoji":"🧪"}} |
| Mode | Input | Command Flag |
|---|---|---|
| Behavioral | RTL Sources | -mode behavioral |
| Post-Synth | post_synth.dcp | -mode functional |
| Post-Impl | post_route.dcp + SDF | -mode timesim |
xvlog src/*.v
xvhdl src/*.vhd
xelab --debug all --snapshot sim_snap work.testbench
xsim sim_snap --R --log xsim.log --wdb sim.wdb
grep -E "ERROR|FAIL|ASSERT|fatal" xsim.log
TCL for xsim:
open_vcd simulation.vcd
log_vcd [get_objects -r /*]
run 1ms
close_vcd
write_verilog -mode timesim -sdf_anno true post_route_sim.v
write_sdf -mode timesim post_route_sim.sdf
Compile with xvlog -d SDF_ANNOTATE.