القائمة
Analyze and fix timing violations. Use when WNS is negative, when asked to close timing, fix setup/hold violations, analyze critical paths, or improve max frequency.
التثبيت باستخدام Codex أو Claude انسخ هذا Prompt والصقه في Codex أو Claude أو مساعد آخر ليراجع صفحة Skill ويثبّتها لك.
استنادا إلى تصنيف SOC المهني
Run a complete Vivado FPGA design flow from RTL sources to bitstream. Use when asked to synthesize, implement, build, or compile an FPGA design. Also handles project creation, checkpoint management, and run orchestration.
Analyze and fix clock domain crossing violations. Use when CDC violations appear, when auditing multi-clock designs, or when reviewing set_false_path and set_max_delay exceptions for safety.
Author and audit Vivado XDC constraint files. Use when creating constraints, finding unconstrained paths, debugging timing exceptions, checking clock definitions, or auditing I/O delays for completeness.
Insert ILA and VIO debug cores into a Vivado design. Use when asked to add hardware debug probes, set up ILA trigger conditions, insert VIO for stimulus injection, or generate .ltx probeinfo files.
Create Pblock floorplan constraints in Vivado. Use when dealing with placement congestion, SSI multi-die devices, reconfigurable partitions (DFX), or when critical paths need physical locality.
Run a complete Vivado design flow: project creation, synthesis, implementation, bitstream. Use when asked to build, synthesize, implement, or compile an FPGA design from RTL sources.
| name | vivado-timing |
| version | 1.0.0 |
| description | Analyze and fix timing violations. Use when WNS is negative, when asked to close timing, fix setup/hold violations, analyze critical paths, or improve max frequency. |
| metadata | {"openclaw":{"requires":{"bins":["vivado"]},"emoji":"⏱️"}} |
open_checkpoint /tmp/vivaclaw_post_route.dcp
report_timing_summary -delay_type min_max -report_unconstrained -check_timing_internal -max_paths 10 -input_pins -file /tmp/vivaclaw_rpt/timing_summary.rpt
report_design_analysis -timing -logic_level_distribution -file /tmp/vivaclaw_rpt/design_analysis.rpt
set p [get_timing_paths -max_paths 1 -slack_lesser_than 0 -delay_type max]
if {$p != ""} {
puts "SLACK: [get_property SLACK $p]"
puts "LOGIC_LEVELS: [get_property LOGIC_LEVELS $p]"
puts "DATAPATH_DELAY: [get_property DATAPATH_DELAY $p]"
}
| Condition | Action |
|---|---|
| Logic Levels > 8 | Re-synth: -directive PerformanceOptimized -retiming |
| Route Delay > 60% | route_design -directive AggressiveExplore |
| Hold Violation | phys_opt_design -directive ExploreWithHoldFix |
| High Fanout (>5k) | set_property MAX_FANOUT 100 [get_cells <driver>] |
| MHz | Max Levels |
|---|---|
| 100 | 16 |
| 200 | 8 |
| 300 | 6 |
| 400 | 4 |
place=WLDrivenPlacement, route=Defaultplace=AltSpreadLogic_high, route=Exploreplace=ExtraNetDelay_high, route=AggressiveExplorephys_opt=AggressiveExplore, route=MoreGlobalIterationsphys_opt=AlternativeFlowWithRetiming, route=AggressiveExplore