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rtl-design

Use when writing or modifying Verilog/SystemVerilog RTL, or recording each child's file layout and constraint annotations; not for verification, lint, or synthesis.

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Source facts

Repository
chipweaver/veripower
Last source activity
August 22, 2026 at 03:01
Detected SKILL.md language
English
Stars
4
Forks
1

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The review-first prompt is selected by default. You can switch to a direct command or download a local copy.

Review the source files

Read SKILL.md and any companion files shown by SkillsMP before deciding whether to install.