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SkillsMP has collected 29 skills from intel/torch-xpu-ops. Open a skill to review its source and details.
Showing 29 of 29 collected skills.
Use when asked to fix a GitHub issue end-to-end, run the agent pipeline on an issue, or process an `agent:active` / batch tracking issue. Orchestrates the full pipeline: `issue-triage` → `fix-reproduce` → `fix-root-cause` → `fix-implement` → `fix-verify` →…
Find upstream PyTorch behavior or fixes that may require XPU parity work, validate them on XPU, and produce independently reviewed evidence. Use for time-window alignment scans or targeted upstream-to-XPU investigations; not for implementing the resulting…
Shallow, text-only triage of a GitHub issue on pytorch or torch-xpu-ops. Classifies the issue and returns a report (markdown table + JSON) for the caller to act on. Read-only; the skill itself does not comment on or label the issue.
Use when asked to implement a fix for a root-caused failure, apply a proposed patch, or produce a staged code change from triage output. Takes fix-root-cause's output and edits code; leaves the change staged (uncommitted) for fix-verify to check. Does NOT run…
Use when asked to verify a fix works, confirm a staged patch resolves a failure, or produce a before/after summary of a fix. Runs the test command against a source build with the fix applied and reports PASSED / FAILED / CANNOT_VERIFY. Called by both…
Use when asked to fix nightly CI failures, analyze a nightly failure report, debug XPU tests from a CI run, or process a batch of failing tests emailed from the nightly job. Runs the same leaf pipeline as `issue-handler` but batches multiple failures using a…
How to create a pull request for the intel/torch-xpu-ops repository. Use when an agent has finished implementing a fix or feature and needs to prepare a branch and PR description that satisfies CI and review requirements.
Analyze a failure and determine root cause, fix strategy, target repo, domain, and verdict (IMPLEMENTING or NEEDS_HUMAN). Analysis-only — no code changes. Used by both issue-handler and xpu-nightly-ci-fix orchestrators.
Use when asked to reproduce a bug, verify a nightly CI failure, or confirm a failure still exists on latest source. Verifies whether a bug still reproduces before an orchestrator commits time to a fix. Runs a three-stage fallback (nightly wheel -> source…
Generate PyTorch release notes worksheet for XPU by searching git log between release branches. Trigger on "xpu-release-notes", "generate XPU release notes".
Analyze UT (unit test) results for a torch-xpu-ops PR. Use when asked to check test results, analyze CI failures, or evaluate test coverage for a PR. Produces a structured report of new failures, failure relevance, and new test coverage.
Review pull requests for XPU operator or backend code. Use when reviewing PRs, when asked to review code changes, or when the user mentions "review PR", "code review", or "check this PR".
Check PyTorch ciflow/xpu (xpu.yml) on the main branch, collect the failing XPU test cases from the most recent completed run(s), analyze the ROOT CAUSE of each failure with AI, and produce a list with a prefilled "disable issue" link per case. USE WHEN the…
Rules for automatically determining which disable_* labels to apply to a PR based on the file paths changed. Used by the auto-label workflow.
Extract GPU ISA from oneDNN ngen-JIT kernels. This is the ONLY codegen path that bypasses the standard SYCL/SPIR-V/IGC stack. oneDNN uses its own native code generator (ngen) that directly emits GPU ISA bytes — no SPIR-V, no IGC, no zebin ELF, no .debug_line.…
Extract GPU ISA from AOT-compiled SYCL binaries using NEO driver runtime dump. Use when the kernel is a SYCL symbol (_ZTS...) from an AOT binary such as libtorch_xpu.so, SYCL-TLA FMHA, or any DPC++ binary compiled with -fsycl-targets=spir64_gen -Xs "-device…
Extract GPU ISA from JIT-compiled SYCL kernels. The binary only contains SPIR-V; IGC compiles it to native ISA at first launch. The zebin only exists in memory at runtime, so IGC_ShaderDumpEnable=1 is required to capture it. Use when extracting ASM from SYCL…
Extract GPU ISA from Triton kernels on XPU. Triton compiles through the same IGC backend as SYCL (Triton IR → SPIR-V → IGC → zebin). Extraction is identical to sycl-jit: IGC_ShaderDumpEnable=1 captures the zebin at runtime. Use when extracting ASM from…
Extract Intel GPU ISA (assembly) from any XPU kernel. Classifies the codegen path (SYCL AOT, SYCL JIT, Triton, or oneDNN ngen) and delegates to the matching extraction skill. Use when asked to extract ASM, disassemble XPU kernels, get GPU ISA for an aten op,…
Map Intel GPU ISA instruction addresses to precise SYCL/DPC++ source file:line numbers. Primary method reads the DWARF .debug_line section from the GPU zebin ELF. Fallback uses structural pattern recognition by opcode mix. Use when mapping ASM to source code,…
Select the Intel GPU device to use when a system has multiple Intel GPU devices. Use this skill when the user wants to run a workload on Intel GPU, mentions device selection, ZE_AFFINITY_MASK, or when multiple Level Zero GPU devices are detected and one must…
Source the Intel oneAPI environment before running workloads that depend on oneAPI, SYCL, DPC++, or Level Zero. Use this skill when the user needs to set up oneAPI, source setvars.sh, configure the Intel compiler environment, or when icpx/sycl-ls are not…
Use tmux to launch and manage long-running jobs that must survive beyond the bash tool timeout. Use this skill when the user mentions long-running commands, background tasks, training jobs, large builds, or any command expected to exceed the bash tool timeout.
Set up Intel GPU unitrace profiling tool. Use this skill whenever the user mentions unitrace, Intel GPU tracing, pti-gpu tracing tool, GPU profiling with unitrace, or wants to build/install unitrace from source. Also trigger when the user asks about tracing…
Use when setting up a new torch-xpu-ops release branch corresponding to a PyTorch release. Covers branch creation, release tracker issue, workflow default changes PR, and tracker comment.
Build PyTorch from source with Intel XPU (GPU) support. Use when the user asks to build PyTorch, set up the XPU build environment, rebuild after code changes, install PyTorch for XPU, or configure oneAPI. Handles prerequisites check, build_pytorch.env setup,…
Generate and analyze T1/T2/R roofline reports for PyTorch OOB workloads comparing Intel XPU and NVIDIA CUDA. Use when working with eager profiling artifacts, per-model reports, fleet summaries, graph consistency, or XPU-vs-CUDA software efficiency analysis.
Convert PyTorch AT_DISPATCH macros to AT_DISPATCH_V2 format in ATen C++ code. Use when porting AT_DISPATCH_ALL_TYPES_AND*, AT_DISPATCH_FLOATING_TYPES*, or other dispatch macros to the new v2 API. For ATen kernel files, CUDA kernels, and native operator…
Guide users through creating Agent Skills for Claude Code. Use when the user wants to create, write, author, or design a new Skill, or needs help with SKILL.md files, frontmatter, or skill structure.