torch-xpu-ops

Analyze UT (unit test) results for a torch-xpu-ops PR. Use when asked to check test results, analyze CI failures, or evaluate test coverage for a PR. Produces a structured report of new failures, failure relevance, and new test coverage.

Rules for automatically determining which disable_* labels to apply to a PR based on the file paths changed. Used by the auto-label workflow.

Extract GPU ISA from oneDNN ngen-JIT kernels. This is the ONLY codegen path that bypasses the standard SYCL/SPIR-V/IGC stack. oneDNN uses its own native code generator (ngen) that directly emits GPU ISA bytes — no SPIR-V, no IGC, no zebin ELF, no .debug_line. Use when extracting ASM from oneDNN kernels (gemm_kernel, gen_conv_kernel), matmul, linear, conv, or SDPA-graph ops dispatched via mkldnn.

Extract GPU ISA from AOT-compiled SYCL binaries using NEO driver runtime dump. Use when the kernel is a SYCL symbol (_ZTS...) from an AOT binary such as libtorch_xpu.so, SYCL-TLA FMHA, or any DPC++ binary compiled with -fsycl-targets=spir64_gen -Xs "-device <gpu>".

Extract GPU ISA from JIT-compiled SYCL kernels. The binary only contains SPIR-V; IGC compiles it to native ISA at first launch. The zebin only exists in memory at runtime, so IGC_ShaderDumpEnable=1 is required to capture it. Use when extracting ASM from SYCL JIT kernels, torch-xpu-ops built with TORCH_XPU_ARCH_LIST=none, or standalone DPC++ without AOT flags.

Extract GPU ISA from Triton kernels on XPU. Triton compiles through the same IGC backend as SYCL (Triton IR → SPIR-V → IGC → zebin). Extraction is identical to sycl-jit: IGC_ShaderDumpEnable=1 captures the zebin at runtime. Use when extracting ASM from torch.compile fusions (triton_per_fused, triton_poi, triton_red), standalone @triton.jit kernels, or Inductor-generated XPU kernels.

Extract Intel GPU ISA (assembly) from any XPU kernel. Classifies the codegen path (SYCL AOT, SYCL JIT, Triton, or oneDNN ngen) and delegates to the matching extraction skill. Use when asked to extract ASM, disassemble XPU kernels, get GPU ISA for an aten op, dump shader for PyTorch XPU, or disassemble a standalone DPC++/Triton binary.

Map Intel GPU ISA instruction addresses to precise SYCL/DPC++ source file:line numbers. Primary method reads the DWARF .debug_line section from the GPU zebin ELF. Fallback uses structural pattern recognition by opcode mix. Use when mapping ASM to source code, finding which source line a GPU instruction comes from, or doing DWARF line table analysis on GPU binaries.

Review pull requests for XPU operator or backend code. Use when reviewing PRs, when asked to review code changes, or when the user mentions "review PR", "code review", or "check this PR".

How to create a pull request for the intel/torch-xpu-ops repository. Use when an agent has finished implementing a fix or feature and needs to prepare a branch and PR description that satisfies CI and review requirements.

Select the Intel GPU device to use when a system has multiple Intel GPU devices. Use this skill when the user wants to run a workload on Intel GPU, mentions device selection, ZE_AFFINITY_MASK, or when multiple Level Zero GPU devices are detected and one must be chosen.

Source the Intel oneAPI environment before running workloads that depend on oneAPI, SYCL, DPC++, or Level Zero. Use this skill when the user needs to set up oneAPI, source setvars.sh, configure the Intel compiler environment, or when icpx/sycl-ls are not found in PATH.

Use tmux to launch and manage long-running jobs that must survive beyond the bash tool timeout. Use this skill when the user mentions long-running commands, background tasks, training jobs, large builds, or any command expected to exceed the bash tool timeout.

Set up Intel GPU unitrace profiling tool. Use this skill whenever the user mentions unitrace, Intel GPU tracing, pti-gpu tracing tool, GPU profiling with unitrace, or wants to build/install unitrace from source. Also trigger when the user asks about tracing Intel GPU workloads with unitrace, profiling SYCL/Level Zero/OpenCL applications on Intel GPUs using unitrace, or setting up pti-gpu tools. This skill handles checking if unitrace is already available, and if not, cloning and building it from source.

Use when setting up a new torch-xpu-ops release branch corresponding to a PyTorch release. Covers branch creation, release tracker issue, workflow default changes PR, and tracker comment.

Scan pytorch/pytorch issues, PRs, and commits (CUDA, ROCm, or any backend) for bugs that may also affect XPU, adapt upstream reproducers for XPU, and validate on local XPU nightly. Use when aligning upstream backend fixes for XPU parity.

Fix a triaged CI failure for pytorch or torch-xpu-ops. Use when an issue already contains a root-cause analysis and a proposed fix strategy, and you need to implement the fix, verify it, and prepare a summary. Handles both unit-test (UT) and end-to-end (E2E) failures, including stale XPU skip-marker removal.

Classify a GitHub issue as bug or nonbug and extract metadata (test_type, category, dependency, platform, context). Use as the first stage of issue handling, when you need a structured classification of an issue's type and key attributes returned as JSON.

End-to-end orchestrator for handling a single GitHub issue on pytorch or torch-xpu-ops. Use when asked to fix the issue — formatting the issue, verifying it reproduces, triaging the root cause, proposing and verifying a fix, and reporting back to the user. Coordinates the issue-format, test-verification, xpu-issues-triaging, and issue-fix sub-skills.

Run a test and report whether a bug still reproduces (before a fix) or is resolved (after a fix). In interactive mode you usually already have the command and just run it; in pipeline mode you resolve a raw CI reference to a local command first.

Triaging the pytorch or torch-xpu-ops issue. Use to determine root cause and fix strategy.

Build PyTorch from source with Intel XPU (GPU) support. Use when the user asks to build PyTorch, set up the XPU build environment, rebuild after code changes, install PyTorch for XPU, or configure oneAPI. Handles prerequisites check, build_pytorch.env setup, build verification, and torch-xpu-ops development pin override.

Analyze nightly CI test failures and fix XPU test cases. Use when the user provides CI failure reports, nightly status emails, failing test names, or asks to "fix nightly failures", "analyze CI failures", or "debug XPU tests". Handles triaging, reproducing, root cause analysis, and applying fixes with verification.

Generate and analyze T1/T2/R roofline reports for PyTorch OOB workloads comparing Intel XPU and NVIDIA CUDA. Use when working with eager profiling artifacts, per-model reports, fleet summaries, graph consistency, or XPU-vs-CUDA software efficiency analysis.

Convert PyTorch AT_DISPATCH macros to AT_DISPATCH_V2 format in ATen C++ code. Use when porting AT_DISPATCH_ALL_TYPES_AND*, AT_DISPATCH_FLOATING_TYPES*, or other dispatch macros to the new v2 API. For ATen kernel files, CUDA kernels, and native operator implementations.

Guide users through creating Agent Skills for Claude Code. Use when the user wants to create, write, author, or design a new Skill, or needs help with SKILL.md files, frontmatter, or skill structure.