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SkillsMP has collected 1,968 skills from MikeTreml/MissionControl. Open a skill to review its source and details.
MikeTreml/MissionControlShowing 40 of 1,968 collected skills.
Expert skill for Prometheus metrics and Grafana dashboards. Write and validate PromQL queries, generate Grafana dashboard JSON, create alerting and recording rules, analyze metric cardinality, and debug scrape configurations.
Enterprise secrets management across platforms. Manage secrets with HashiCorp Vault, AWS Secrets Manager, Azure Key Vault, GCP Secret Manager, and Kubernetes secrets. Configure rotation, policies, and access controls.
Service mesh configuration and operations expertise for Istio, Linkerd, and Consul Connect
Specialized skill for Terraform and Infrastructure as Code operations. Execute terraform commands, validate HCL, analyze state and drift, generate modules, and support multi-cloud providers (AWS, GCP, Azure).
Deep expertise in ARM Cortex-M architecture and peripherals
CAN/CAN-FD bus analysis and development expertise
Embedded cryptographic operations and secure element integration. Expert skill for hardware crypto accelerators, secure key storage, TrustZone configuration, and side-channel attack mitigation.
Embedded firmware documentation generation and maintenance using Doxygen and related tools. Expert skill for API documentation, hardware interface documentation, memory maps, and integration with documentation systems.
Expert skill for FreeRTOS configuration, debugging, and optimization
Deep integration with JTAG/SWD debug probes for hardware-level debugging and flash programming
GNU linker script generation and optimization for embedded systems. Expert skill for memory layout definition, section placement, multi-image linking, and memory protection configuration.
Embedded memory analysis, optimization, and leak detection
MISRA C compliance checking and static analysis integration
Motor control algorithms and driver implementation
Nordic Semiconductor nRF5x/nRF Connect SDK expertise
Over-the-air firmware update implementation expertise for embedded systems. Expert skill for delta updates, image signing, update protocols, partition management, and rollback mechanisms.
Power consumption measurement and analysis expertise for embedded systems. Integrates with power analyzer tools to measure, profile, and optimize power consumption in battery-powered and energy-efficient designs.
Serial protocol analysis and debugging for common embedded interfaces (I2C, SPI, UART)
Test equipment integration for signal analysis (oscilloscope and logic analyzer)
STMicroelectronics STM32 HAL and Low-Level driver expertise
Embedded unit testing with Unity framework and CMock
USB device and host stack implementation expertise
Embedded wireless protocol implementation (LoRa, Zigbee, Thread, Matter)
Specialized skill for Zephyr RTOS development and configuration
Expert skill for AMBA AXI protocol implementation and verification in FPGA designs
Specialized skill for clock domain crossing analysis and synchronizer design in FPGA designs
Formal property verification and model checking skill for FPGA designs
On-chip debugging skill with ILA, VIO, and related FPGA debug tools
Specialized skill for finite state machine design and optimization in FPGAs
Multi-simulator expertise for functional verification of FPGA designs
Expert skill for C/C++ to RTL conversion using High-Level Synthesis tools
Vendor IP core configuration and integration expertise for FPGA designs
Expert skill for on-chip and external memory interface design in FPGAs
Expert skill for FPGA place and route optimization and physical implementation
FPGA power estimation and optimization skill for low-power design
RTL code quality checking and linting. Runs lint rules, identifies synthesis issues, detects inferred latches, and generates lint reports with waivers.
Specialized skill for creating and debugging SystemVerilog assertions for FPGA verification
Expertise in RTL optimization for FPGA synthesis tools. Analyzes synthesis reports, applies attributes, and guides resource inference for optimal QoR.
Expert skill for developing and validating timing constraints. Writes SDC (Synopsys Design Constraints) and XDC files for FPGA timing closure.
Deep expertise in Universal Verification Methodology (IEEE 1800.2) for FPGA verification