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Compile a named Chisel module to Verilog using sbt, outputting to the module's workspace directory.
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| name | compile |
| description | Compile a named Chisel module to Verilog using sbt, outputting to the module's workspace directory. |
| disable-model-invocation | true |
| allowed-tools | ["Bash","Read"] |
Compile a Chisel module to Verilog, placing output in the module's workspace directory.
/chip-agent:compile <ModuleName>
Extract module name from $ARGUMENTS. If empty or blank, ask the user: "Which module should I compile? Please provide a PascalCase module name (e.g., ALU, Counter, TrivialModule)."
Validate module name. The name must be PascalCase: first character uppercase, no spaces, no hyphens, only alphanumeric characters. If invalid, inform the user and ask for a corrected name.
Determine the project root directory by finding the nearest ancestor directory of this skill file that contains .claude. Use that directory as the base for all paths below.
Run compilation. Execute the compile script with the workspace path:
<project-root>/scripts/compile.sh workspace/<ModuleName>
On success: List the generated files in workspace/<ModuleName>/generated/ so the user can see what was produced. Mention that they can now run /chip-agent:lint <ModuleName> to check the output.
On failure: Show the build error output. Suggest checking the Chisel source at chisel-project/src/main/scala/chipagent/<ModuleName>.scala for issues.
$ARGUMENTS -- A PascalCase module name (e.g., ALU, Counter, TrivialModule).
Generated Verilog files in workspace/<ModuleName>/generated/ (.v and .sv files).
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