sar-adc-skills

Use this skill for SAR ADC system design and all its key building blocks. Covers: SAR ADC architecture, CDAC operation and switching schemes, sync/async SAR logic, top-plate vs bottom-plate sampling, noise and ENOB budgeting, redundancy, PVT, metastability, peripheral design, and Verilog-A modeling. Also covers the core analog submodules needed for a complete SAR ADC: StrongArm dynamic comparator (topology, noise, offset, sizing), bootstrapped sampling switch (circuit operation, Ron flatness, sizing), and LDO regulator for clean ADC supply (topology, PSRR, compensation, sizing). Includes the SAR_11B_ZZS taped-out 11-bit reference design (TSMC 28nm HPC+). Also covers Spectre simulation setup, ENOB/SNDR measurement with ADCToolbox, and a phased verification flow (behavioral → hybrid → full transistor-level). Use for any question about SAR ADC design from specs to first-order block decisions, submodule sizing guidance, simulation/verification, or reference design lookup.