anlogic-modelsim

name	anlogic-modelsim
description	Use when Anlogic FPGA verification inputs are ready and Codex needs to run ModelSim, organize `run.do` plus `wave.do`, preserve waveform artifacts, export `.vcd` from `.wlf`, and produce a pass/fail/block conclusion that is valid for downstream waveform extraction and signal comparison.

Anlogic FPGA ModelSim Simulation Analysis Skill

Use this skill after anlogic-testbench and before anlogic-wave-signal-analyzer.

Role

Turn verification inputs into a clear pass, fail, or blocked simulation conclusion with preserved waveform artifacts.

Inputs

• the latest doc/stage-S2-summary.md
• testbench top
• stimulus and checker logic
• pass/fail criteria
• required compile order
• run.do and wave.do inputs

Boundaries

• do not rewrite RTL design intent directly
• do not create the TD project
• do not treat script success as proof that function correctness is proven

Outputs

• pass/fail/block conclusion
• preserved waveform artifacts
• doc/stage-S3-summary.md

Not Doing

• not forwarding full transcripts when a compact artifact summary is enough

Upstream Inputs

Prefer inputs from anlogic-testbench:

• testbench top
• stimulus and checker logic
• pass/fail criteria
• required compile order
• run.do and wave.do inputs

If these inputs are incomplete, route back to anlogic-testbench instead of forcing a simulation conclusion.

Responsibilities

• Organize vlog compile order and simulation library mapping
• Generate or repair run.do and wave.do
• Run ModelSim and state whether the result is pass, fail, or blocked
• Preserve simulation artifacts for downstream extraction and comparison
• Export .vcd from .wlf when the downstream flow needs waveform analysis
• Judge whether failures belong to script setup, testbench input quality, or RTL design assumptions

Not Responsible For

• Do not rewrite RTL design intent directly
• Do not create the TD project
• Do not treat script success as proof that function correctness is proven

Fixed Paths

• ModelSim: D:/work/Modelsim/2020.4/win64/modelsim.exe
• Typical Anlogic simulation libraries: D:/work/Modelsim/2020.4/anlogic/621
• TD references: D:/work/TD/6.2.1/template and D:/work/TD/6.2.1/sim_release

Standard Workflow

1. Confirm testbench deliverables and pass/fail criteria are complete.
2. Prepare ordered compile commands and library mapping.
3. Ensure run.do calls wave.do.
4. Run simulation and preserve work/, transcript, and .wlf.
5. If waveform comparison is required, export .vcd from .wlf.
6. Decide whether the stage is pass, fail, or blocked.
7. Hand off to anlogic-wave-signal-analyzer only when the waveform artifacts are usable.

Required Artifacts

Every handoff-ready simulation directory must preserve:

• compile.f when that file is part of the project flow
• run.do
• wave.do
• work/
• transcript
• vsim.wlf or a renamed <case>.wlf

Do not auto-delete these artifacts at the end of the run.

WLF And VCD Rules

• Always keep the .wlf artifact after simulation.
• Default filename is vsim.wlf, but a clearer <case>.wlf name is allowed.
• When the next stage needs signal extraction, export .vcd with:

wlf2vcd -o .\wave.vcd .\vsim.wlf

• The simulation conclusion must explicitly say:
  • whether .wlf was preserved
  • whether .vcd was exported successfully
  • where the artifacts were saved
  • whether the flow may enter anlogic-wave-signal-analyzer

Handoff Gate

Do not release this stage unless all of the following are true:

• compilation and load status are known
• pass/fail/block status is stated
• artifact freshness is stated
• .wlf retention is confirmed
• .vcd export status is stated when waveform analysis is expected
• fixed summary fields:
  • current_stage
  • goal
  • confirmed_constraints
  • artifacts
  • decision
  • blocking_reason
  • next_action

Routing Rules

• Missing stimulus, checker, or pass/fail criteria: go back to anlogic-testbench
• Missing simulation models, compile list, or library mapping: go back to anlogic-testbench
• RTL structure, interface, or primitive assumptions are wrong: go back to anlogic-code-design
• .wlf missing or .vcd export unusable: stay in this skill until artifacts are usable
• Simulation and waveform artifacts are ready: hand off to anlogic-wave-signal-analyzer

Strong Rules

• Keep the user-preferred script style when a known run.do, test.do, or grouped wave.do style already exists.
• Do not add default cleanup such as vdel -lib work -all.
• A simulation handoff is incomplete if wave.do is missing or unusable.
• A project must not proceed to anlogic-project-creation until the later anlogic-signal-comparison stage also passes.

References

• references/simulation-stage-map.md
• references/modelsim_config.md
• references/report_template.md
• references/wave-artifact-handoff.md

2026-05-06 Rule: Local Anlogic Library And Sim Resource Completeness

• Do not treat a simulation directory as handoff-ready if it depends on accidental global ModelSim mappings that are not preserved in the project.
• Prefer a project-local modelsim.ini or equivalent local mapping file when vendor libraries such as common, ph1p, or other Anlogic primitive libraries are required.
• If the transcript shows unresolved glbl, PH1P_* primitives, or similar vendor primitive load failures, keep the issue in this skill and repair library mapping before routing back to RTL.
• If the design depends on side resources such as DDR PHY ROM text or memory-init collateral, preserve those files in the simulation project and call them out explicitly in the stage conclusion.
• A stage conclusion must say whether vendor-library mapping was localized successfully and whether all required sim side resources were present.