hardware-aware-qaoa-cybersecurity

name	hardware-aware-qaoa-cybersecurity
description	Hardware-aware QAOA methodology for cybersecurity applications. Combines hardware noise modeling, error-mitigated expectation estimation, and application-specific problem formulation for 100+ qubit NISQ processors.
metadata	{"arxiv_id":"2606.09469","published":"2026-06-08"}

Hardware-Aware QAOA for Cybersecurity

Core Concepts

QAOA on real NISQ hardware requires accounting for device-specific noise, connectivity, and calibration drift. This paper demonstrates hardware-aware QAOA on 100+ qubit IBM processors for honeypot traffic partitioning.

Methodology

Hardware-Aware Problem Formulation

1. Map cybersecurity problem to QUBO: Formulate honeypot traffic partitioning as QUBO
2. Hardware topology awareness: Account for qubit connectivity constraints
3. Noise-aware circuit design: Incorporate device-specific error rates into compilation

Error-Mitigated Expectation Estimation

1. Readout error mitigation: Apply measurement error mitigation using calibration data
2. Zero-noise extrapolation: Scale circuit noise and extrapolate to zero-noise limit
3. Sampling optimization: Use efficient sampling strategies to reduce shot count

Activation Keywords

• hardware-aware qaoa
• honeypot traffic partitioning
• cybersecurity quantum optimization
• QAOA on real hardware
• noise-aware quantum algorithm
• NISQ QAOA deployment

Pitfalls

• Hardware calibration drift degrades QAOA performance between calibrations
• SWAP gates for non-connected qubits increase circuit depth exponentially
• Shot count scales as O(1/epsilon^2) for epsilon precision
• 100+ qubit problems require careful qubit selection based on connectivity graph