| name | rescom-reconfigurable-snn-stochastic-computing |
| description | ReSCom: A Reconfigurable Spiking Neural Network Accelerator Using Stochastic Computing. Neuromorphic hardware architecture for energy-efficient SNN inference with runtime accuracy-latency-energy trade-offs. |
| version | 1 |
| authors | ["Ali Alipour Fereidani","Mohammad Rasoul Roshanshah","Saeed Safari"] |
| arxiv_id | 2606.13560 |
| date_published | 2026-06-11 |
| categories | ["cs.AR","cs.NE","neuromorphic","hardware","stochastic-computing"] |
| tags | ["spiking neural networks","FPGA","stochastic computing","energy-efficient","hardware accelerator","reconfigurable","IF neuron","LIF neuron","synaptic neuron model"] |
| keywords | ["ReSCom","stochastic computing","SNN accelerator","neuromorphic hardware","FPGA","energy-efficient inference","reconfigurable neuron","hardware optimization"] |
| trigger_words | ["ReSCom","stochastic computing SNN","reconfigurable SNN accelerator","SNN hardware","neuromorphic FPGA","energy-efficient spiking","stochastic arithmetic"] |
| related_skills | ["snn-performance-analysis","snn-fpga-hardware-software-codesign","snn-quantized-dynamics-integer","stochastic-quantum-neural-network"] |
ReSCom: A Reconfigurable Spiking Neural Network Accelerator Using Stochastic Computing
Core Innovation
Stochastic computing for SNN hardware realization: ReSCom addresses the fundamental challenge of implementing SNNs on hardware - neuronal computations incur significant power/area costs, and approximate arithmetic destabilizes recurrent state updates. The solution uses stochastic arithmetic for multiplication operations while preserving exact fixed-point addition/subtraction.
Key novelty: Runtime trade-offs between accuracy, latency, and energy consumption via stochastic bit-stream length control.
Methodology Details
1. Stochastic Arithmetic Strategy
Principle:
- Multiplication → stochastic bit-stream operations (reduced hardware complexity)
- Addition/Subtraction → exact fixed-point arithmetic (maintains stability for recurrent state updates)
Implementation:
# Stochastic multiplication for neuronal dynamics
stochastic_mul(a, b):
- Encode a and b as stochastic bit-streams
- AND operation: output = a AND b (probability preserves product)
- Bit-stream length L determines accuracy vs. latency trade-off
# Fixed-point addition (exact)
exact_add(a, b):
- Preserve deterministic computation for membrane potential updates
- Prevent destabilization in recurrent SNN state dynamics
Why this works:
- Multiplication dominates neuron computation cost (synaptic weight × input)
- Addition/subtraction critical for membrane potential integration - must remain exact
- Stochastic computing reduces hardware area/power for multiplications significantly
2. Reconfigurable Neuron Design
Unified architecture supporting 3 neuron models:
- Integrate-and-Fire (IF)
- Leaky Integrate-and-Fire (LIF)
- Synaptic Neuron Model
Reconfiguration mechanism:
- Runtime parameter configuration (no hardware re-synthesis needed)
- Single hardware block supports all 3 models via control signals
3. Hardware Architecture (FPGA Implementation)
Platform: Xilinx Artix-7 FPGA
Performance metrics (MNIST inference):
- Accuracy: 92.80%
- Energy: 0.05 mJ per image at 100 MHz
- Latency: Configurable via stochastic bit-stream length L
- Power efficiency: Outperforms recent state-of-the-art SNN accelerators
