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SkillsMP ha recopilado 15 skills de Arcadia-1/analog-agents. Abre una skill para revisar su origen y sus detalles.
Mostrando 15 de 15 skills recopiladas.
Crawl and analyze post-layout parasitic netlists without running SPICE. Answers "what's the effective resistance from node A to node B across this massive R mesh?", "inside the VREFN mesh, which device pins are electrically farthest apart?", "which nets have…
Idioma del texto original: inglés
ADC characterization orchestrator in the analog-agents project. Takes simulated/measured ADC output, produces the standard specs bundle (SNDR/SFDR/THD/ENOB, INL/DNL, FOM, NTF where applicable) as a verifier-report, and hands off back to the design/sizing…
Idioma del texto original: inglés
Pre-simulation review and Spectre simulation verification for analog circuits. Reviews circuit netlist and testbench, runs simulation, produces margin report. Use after analog-design completes a netlist.
Idioma del texto original: inglés
Move, clone, package, archive, split, or reorganize Cadence Virtuoso cells and libraries at the design-data level. Use this skill whenever the user wants to: copy a TB to another library, reproduce a sim independently in a fresh library, hand off a design,…
Idioma del texto original: inglés
Self-evolution engine for analog-agents. Reviews completed design sessions to extract lessons, discover new anti-patterns, propose checklist additions, and refine agent prompts. Run after design convergence or project completion. TRIGGER on: "evolve", "what…
Idioma del texto original: inglés
MANDATORY — MUST load this skill when the user mentions: OTA, ADC, PLL, comparator, bandgap, LDO, amplifier, opamp, or any analog/mixed-signal IC design task. Full analog design pipeline: spec -> architecture -> design -> verify -> deliver. Orchestrates…
Idioma del texto original: inglés
Audit analog circuit netlists for correctness, quality, and risks. Supports both pre-layout (schematic) and post-layout (extracted) netlists. Post-layout mode filters massive parasitic netlists before auditing. Works without EDA. TRIGGER on: "audit", "review…
Idioma del texto original: inglés
Explore analog design space without simulation. Compare topologies, sweep parameters with hand calculations, find theoretical limits and Pareto tradeoffs. Use for architecture selection, initial sizing, or understanding design space before committing to EDA…
Idioma del texto original: inglés
Interactive analog design learning companion. Explains circuit design decisions step by step with underlying physics. Use when learning analog design, studying a topology, or wanting detailed explanations of design tradeoffs. TRIGGER on: "teach me",…
Idioma del texto original: inglés
Cross-model circuit design review with divergence analysis. Sends netlist and rationale to multiple external LLMs for independent audit. Supports minimax-m2.7, qwen-3.6-plus, kimi-k2.5, glm-5.1. Use after analog-design to get independent review before…
Idioma del texto original: inglés
Transistor-level circuit design for one analog sub-block. Produces Spectre netlist with hand-calculation rationale. Use when designing a specific circuit block after architecture is defined.
Idioma del texto original: inglés
Knowledge graph for analog circuit design. Stores topologies, strategies, corner lessons, anti-patterns, and project cases. Query with consult, add entries, track relationships, archive project cases. Use to build and query design knowledge across projects.
Idioma del texto original: inglés
Architect Phase 1: decompose top-level analog spec into sub-block specs. Use when starting a new analog design to select architecture, allocate budgets, define sub-block specs, write testbenches, and create verification plans.
Idioma del texto original: inglés
Architect Phase 3: replace behavioral models with verified transistor netlists and run top-level integration verification. Use after all sub-blocks pass L2.
Idioma del texto original: inglés
Architect Phase 2: build Verilog-A behavioral models and validate system architecture. Use after analog-decompose to verify top-level specs are achievable before transistor design.
Idioma del texto original: inglés