Ejecuta cualquier Skill en Manus
con un clic

Ejecuta cualquier Skill en Manus con un clic

vivado-debug

Estrellas3

Forks0

Actualizado22 de abril de 2026 a las 23:03

Insert ILA and VIO debug cores into a Vivado design. Use when asked to add hardware debug probes, set up ILA trigger conditions, insert VIO for stimulus injection, or generate .ltx probeinfo files.

Instalación

Instalar con Codex o Claude Copia este prompt, pégalo en Codex, Claude u otro asistente, y deja que revise la página de la skill y la instale por ti.

Ejecutar en Manus

Fuente

devansh0703

devansh0703/vivaclaw-agent

Abrir repositorio de GitHub Ver repositorios del creador

Descarga

Ejecutar en Manus

Ocupaciones relacionadasSOC

Basado en la clasificación ocupacional SOC

Desarrolladores de softwareOcupaciones informáticas y matemáticas·SOC 15-1252

SKILL.md

readonly

name	vivado-debug
version	1.0.0
description	Insert ILA and VIO debug cores into a Vivado design. Use when asked to add hardware debug probes, set up ILA trigger conditions, insert VIO for stimulus injection, or generate .ltx probeinfo files.
metadata	{"openclaw":{"requires":{"bins":["vivado"]},"emoji":"🔬"}}

Vivado Debug Runbook

1. Pre-insertion Budget

Check BRAM availability. Each ILA uses BRAM: Samples * ProbeWidth / 18432 = BRAM Blocks Abort if utilization > 85%.

2. ILA Depth Recommendation

Frequency	Depth
<100 MHz	4096+
100-250 MHz	2048
>250 MHz	1024

3. ILA Insertion TCL

create_debug_core u_ila_0 ila
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property port_width 1 [get_debug_ports u_ila_0/clk]
connect_debug_port u_ila_0/clk [get_nets sys_clk]

set_property port_width 8 [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {data[*]}]]

4. VIO Insertion TCL

create_debug_core u_vio_0 vio
set_property C_PROBE_OUT0_WIDTH 1 [get_debug_cores u_vio_0]
connect_debug_port u_vio_0/probe_out0 [get_nets reset_vio]

5. Finalization

implement_debug_cores
route_design
write_bitstream debug_run.bit
write_debug_probes -force debug_run.ltx

Note: .bit and .ltx must be used together in Hardware Manager.

Más de este repositorio

mismo repositorio

vivado-flow

devansh0703/vivaclaw-agent

Run a complete Vivado FPGA design flow from RTL sources to bitstream. Use when asked to synthesize, implement, build, or compile an FPGA design. Also handles project creation, checkpoint management, and run orchestration.

2026-04-223

vivado-cdc

devansh0703/vivaclaw-agent

Analyze and fix clock domain crossing violations. Use when CDC violations appear, when auditing multi-clock designs, or when reviewing set_false_path and set_max_delay exceptions for safety.

2026-04-223

vivado-constraints

devansh0703/vivaclaw-agent

Author and audit Vivado XDC constraint files. Use when creating constraints, finding unconstrained paths, debugging timing exceptions, checking clock definitions, or auditing I/O delays for completeness.

2026-04-223

vivado-floorplan

devansh0703/vivaclaw-agent

Create Pblock floorplan constraints in Vivado. Use when dealing with placement congestion, SSI multi-die devices, reconfigurable partitions (DFX), or when critical paths need physical locality.

2026-04-223

vivado-flow

devansh0703/vivaclaw-agent

Run a complete Vivado design flow: project creation, synthesis, implementation, bitstream. Use when asked to build, synthesize, implement, or compile an FPGA design from RTL sources.

2026-04-223

vivado-impl

devansh0703/vivaclaw-agent

Run Vivado implementation phases: opt_design, place_design, phys_opt_design, route_design. Use when asked to run implementation, choose implementation directives, or re-run specific implementation phases.

2026-04-223

name	vivado-debug
version	1.0.0
description	Insert ILA and VIO debug cores into a Vivado design. Use when asked to add hardware debug probes, set up ILA trigger conditions, insert VIO for stimulus injection, or generate .ltx probeinfo files.
metadata	{"openclaw":{"requires":{"bins":["vivado"]},"emoji":"🔬"}}

Vivado Debug Runbook

1. Pre-insertion Budget

Check BRAM availability. Each ILA uses BRAM: Samples * ProbeWidth / 18432 = BRAM Blocks Abort if utilization > 85%.

2. ILA Depth Recommendation

Frequency	Depth
<100 MHz	4096+
100-250 MHz	2048
>250 MHz	1024

3. ILA Insertion TCL

create_debug_core u_ila_0 ila
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property port_width 1 [get_debug_ports u_ila_0/clk]
connect_debug_port u_ila_0/clk [get_nets sys_clk]

set_property port_width 8 [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {data[*]}]]

4. VIO Insertion TCL

create_debug_core u_vio_0 vio
set_property C_PROBE_OUT0_WIDTH 1 [get_debug_cores u_vio_0]
connect_debug_port u_vio_0/probe_out0 [get_nets reset_vio]

5. Finalization

implement_debug_cores
route_design
write_bitstream debug_run.bit
write_debug_probes -force debug_run.ltx

Note: .bit and .ltx must be used together in Hardware Manager.