Menú
SkillsMP ha recopilado 20 skills de xsw632/ChipAgent. Abre una skill para revisar su origen y sus detalles.
Mostrando 20 de 20 skills recopiladas.
Run full Chipyard-to-ORFS PnR flow for large designs (SmallBOOM etc.) using All-Mock memory blackboxing in Docker: generate RTL, preprocess nosram, run multi-round ORFS synth->finish with mock SRAMs to avoid OOM.
Idioma del texto original: inglés
Docker Chipyard flow: generate RTL from a Chipyard config via Docker, run SRAM mapping, stage artifacts into MyDesign, and hand off to PnR.
Idioma del texto original: inglés
Run full Chipyard-to-ORFS PnR flow with multi-round parameter iteration in Docker: generate RTL from Chipyard Docker, preprocess nosram+SRAM override, run 3 rounds of ORFS synth→finish on sky130hd with progressive clock/utilization/density tuning for optimal…
Idioma del texto original: inglés
Run full Chipyard-to-ORFS PnR flow with multi-round parameter iteration: generate RTL from Chipyard with ENABLE_YOSYS_FLOW, preprocess nosram+SRAM override, run 3 rounds of ORFS synth→finish on sky130hd with progressive clock/utilization/density tuning for…
Idioma del texto original: inglés
Unified Chipyard PnR flow: automatically routes to local or Docker workflow based on backend_mode setting.
Idioma del texto original: inglés
Unified Chipyard flow: automatically routes to local or Docker workflow based on backend_mode setting.
Idioma del texto original: inglés
Sync modified files from a ChipAgent local project (e.g. ChipAgent-Test) back to the ChipAgent source repo. Scans all mapped directories, diffs each file, presents a summary table, and asks user which items to copy back.
Idioma del texto original: inglés
Local Chipyard flow: generate RTL from a local Chipyard installation, run SRAM mapping, stage artifacts into MyDesign, and hand off to PnR.
Idioma del texto original: inglés
Generate Verilog RTL from a local Chipyard installation. Elaborates a Rocket Chip config (e.g. TinyRocketConfig) and produces split Verilog files with memory configuration.
Idioma del texto original: inglés
Compile a named Chisel module to Verilog using sbt, outputting to the module's workspace directory.
Idioma del texto original: inglés
Analyze simulation failures by cross-referencing workspace artifacts and producing a structured debug report with fix suggestions.
Idioma del texto original: inglés
Turn a natural language hardware description into Chisel source files. Parses requirements, confirms spec, and generates Scala code (no compile/lint/sim).
Idioma del texto original: inglés
Detect local toolchain versions and write .chipagent/env.json with capability flags. Updates CLAUDE.md Tech Stack table with detected versions.
Idioma del texto original: inglés
Run Verilator lint checks on generated Verilog for a named module in its workspace directory.
Idioma del texto original: inglés
Run ORFS make flow on sky130hd for synthesis, place-and-route, and GDS export. Produces timing/power/area reports and GDS file.
Idioma del texto original: inglés
Parse natural language hardware descriptions into structured JSON specifications, writing the result to workspace/<ModuleName>/spec.json.
Idioma del texto original: inglés
Run Verilator simulation for a named module using its workspace testbench and generated Verilog.
Idioma del texto original: inglés
Analyze Verilog RTL to identify SRAM macro instances and determine their mapping to sky130hd process SRAM macros or standard-cell alternatives.
Idioma del texto original: inglés
Generate a C++ Verilator testbench from a module's spec.json, reading the spec from the workspace directory.
Idioma del texto original: inglés
Full auto-toolchain: parse, generate Chisel, compile, lint, testbench, simulate, report.
Idioma del texto original: inglés