Menú
Run Verilator simulation for a named module using its workspace testbench and generated Verilog.
Instalar con Codex o Claude Copia este prompt, pégalo en Codex, Claude u otro asistente, y deja que revise la página de la skill y la instale por ti.
Basado en la clasificación ocupacional SOC
Run full Chipyard-to-ORFS PnR flow for large designs (SmallBOOM etc.) using All-Mock memory blackboxing in Docker: generate RTL, preprocess nosram, run multi-round ORFS synth->finish with mock SRAMs to avoid OOM.
Docker Chipyard flow: generate RTL from a Chipyard config via Docker, run SRAM mapping, stage artifacts into MyDesign, and hand off to PnR.
Run full Chipyard-to-ORFS PnR flow with multi-round parameter iteration in Docker: generate RTL from Chipyard Docker, preprocess nosram+SRAM override, run 3 rounds of ORFS synth→finish on sky130hd with progressive clock/utilization/density tuning for optimal PPA.
Run full Chipyard-to-ORFS PnR flow with multi-round parameter iteration: generate RTL from Chipyard with ENABLE_YOSYS_FLOW, preprocess nosram+SRAM override, run 3 rounds of ORFS synth→finish on sky130hd with progressive clock/utilization/density tuning for optimal PPA.
Unified Chipyard PnR flow: automatically routes to local or Docker workflow based on backend_mode setting.
Unified Chipyard flow: automatically routes to local or Docker workflow based on backend_mode setting.
| name | simulate |
| description | Run Verilator simulation for a named module using its workspace testbench and generated Verilog. |
| disable-model-invocation | true |
| allowed-tools | ["Bash","Read"] |
Run a Verilator simulation for a named module, executing its C++ testbench against the generated Verilog.
/chip-agent:simulate <ModuleName>
Extract module name from $ARGUMENTS. If empty or blank, ask the user: "Which module should I simulate? Please provide a PascalCase module name (e.g., ALU, Counter, TrivialModule)."
Check prerequisites. Two conditions must be met:
workspace/<ModuleName>/generated/ must exist and contain at least one .v file. If not, tell the user: "No generated Verilog found. Please run /chip-agent:compile <ModuleName> first."workspace/<ModuleName>/sim/tb_<ModuleName>.cpp must exist. If not, tell the user: "No testbench found. Please run /chip-agent:testbench <ModuleName> first to generate one."Determine the project root directory by finding the nearest ancestor directory of this skill file that contains .claude. Use that directory as the base for all paths below.
Run simulation. Execute the simulate script with the workspace path:
<project-root>/scripts/simulate.sh workspace/<ModuleName>
On success (exit 0): Read workspace/<ModuleName>/sim/logs/sim_result.log and present the results in a formatted summary: total tests, pass count, fail count, and per-test breakdown.
On failure (non-zero exit): Read workspace/<ModuleName>/sim/logs/sim_result.log for failure details. Suggest checking the testbench at workspace/<ModuleName>/sim/tb_<ModuleName>.cpp or the Chisel source at chisel-project/src/main/scala/chipagent/<ModuleName>.scala.
$ARGUMENTS -- A PascalCase module name (e.g., ALU, Counter, TrivialModule).
Simulation results from workspace/<ModuleName>/sim/logs/sim_result.log, formatted as a pass/fail summary with per-test breakdown.