fnw

Autonomous iterative research loop. Takes a topic, runs web searches, fetches sources, synthesizes findings, and files everything into the wiki as structured pages. Based on Karpathy's autoresearch pattern: program.md configures objectives and constraints, the loop runs until depth is reached, output goes directly into the knowledge base. Triggers on: "/autoresearch", "autoresearch", "research [topic]", "deep dive into [topic]", "investigate [topic]", "find everything about [topic]", "research and file", "go research", "build a wiki on".

Visual layer of the wiki. Add images, text cards, PDFs, and wiki pages to Obsidian canvas files with auto-positioning inside zones. Integrates with /banana for image capture. Triggers on: /canvas, canvas new, canvas add image, canvas add text, canvas add pdf, canvas add note, canvas zone, canvas list, canvas from banana, add to canvas, put this on the canvas, open canvas, create canvas.

Use when running RTL lint checks. Triggers on 'lint', 'verilator', 'verible', 'spyglass', '语法检查', '可综合性', '组合环路', 'latch检查', 'rtl lint', 'lint检查'. Supports multiple EDA tools with auto-detection.

Use when processing vc-spyglass lint log output to resolve violations. Maps lint rules to JMTAG execution levels, proposes RTL fixes or generates waive files. Triggered by keywords like spyglass, lint log, lint violation, JMTAG, waive file, lint rules.

Use when generating comprehensive SDC timing constraints from FS/microarch documents. Triggers on '生成SDC', 'SDC约束', 'timing constraints', '时序约束文件', 'write SDC', 'SDC文件'. Produces production-quality SDC covering clocks, I/O, design rules, timing exceptions, and area/power constraints.

Use when running SpyGlass CDC checks on RTL. Triggers on 'cdc检查', 'cdc check', 'spyglass cdc', '跨时钟域检查', 'cdc验证', 'clock domain crossing', 'cdc setup', 'cdc_verify'. Generates SGDC constraints, runs CDC goals, produces violation reports.

Use when processing SpyGlass CDC reports to resolve violations. Triggers on 'cdc违例', 'cdc violation', 'cdc report', 'cdc分析', 'cdc waive', 'cdc修复', 'cdc resolver'. Maps CDC rules to priority levels, proposes RTL fixes or generates waiver files.

Use when running SpyGlass RDC checks on RTL. Triggers on 'rdc检查', 'rdc check', 'spyglass rdc', '复位域交叉检查', 'rdc验证', 'reset domain crossing', 'rdc setup', 'rdc_verify'. Generates RDC constraints, runs RDC goals, produces violation reports.

Use when processing SpyGlass RDC reports to resolve violations. Triggers on 'rdc违例', 'rdc violation', 'rdc report', 'rdc分析', 'rdc waive', 'rdc修复', 'rdc resolver'. Maps RDC rules to priority levels, proposes RTL fixes or generates waiver files.

Strip clutter from web pages before ingesting into the wiki. Removes ads, navigation, headers, footers, and boilerplate: leaving clean readable markdown that saves 40-60% tokens. Triggers on: defuddle, clean this page, strip this url, fetch and clean, clean web content before ingesting, strip ads, remove clutter, clean URL content, readable markdown from URL.

Create stunning, animation-rich HTML presentations from scratch or by converting PowerPoint files. Use for solution decks, presales/sales pitches, client proposals, pitch decks, teaching tutorials, conference talks, and internal presentations. Ideal for sales and presales teams. Helps non-designers discover their aesthetic through visual exploration rather than abstract choices.

Create and edit Obsidian Bases (.base files): Obsidian's native database layer for dynamic tables, card views, list views, filters, formulas, and summaries over vault notes. Triggers on: create a base, add a base file, obsidian bases, base view, filter notes, formula, database view, dynamic table, task tracker base, reading list base.

Write correct Obsidian Flavored Markdown: wikilinks, embeds, callouts, properties, tags, highlights, math, and canvas syntax. Reference this when creating or editing any wiki page. Triggers on: write obsidian note, obsidian syntax, wikilink, callout, embed, obsidian markdown, wikilink format, callout syntax, embed syntax, obsidian formatting, how to write obsidian markdown.

Generate high-quality technical HTML presentations (Reveal.js) and Markdown technical deep-dive articles from projects or papers. Covers architecture diagrams, code walkthroughs, math formulas, and speaker notes. Use when users say: 'make a presentation', 'create slides', 'generate HTML slides', 'technical presentation', 'paper presentation', 'Reveal.js slides', 'write a technical deep-dive article', 'create tech blog from code', 'generate architecture diagrams with matplotlib'. Triggers on requests to: (1) Convert a project/paper into an HTML slide deck, (2) Write a Markdown technical analysis article, (3) Generate matplotlib architecture diagrams for documentation.

Save the current conversation, answer, or insight into the Obsidian wiki vault as a structured note. Analyzes the chat, determines the right note type, creates frontmatter, files it in the correct wiki folder, and updates index, log, and hot cache. Triggers on: "save this", "save that answer", "/save", "file this", "save to wiki", "save this session", "file this conversation", "keep this", "save this analysis", "add this to the wiki".

Rollup of wiki log entries into meta-pages. Reads the last 2^k entries from wiki/log.md, writes a structurally-idempotent fold page to wiki/folds/ that links back to children. Extractive summarization (no invention). Dry-run by default, stdout-only; commit mode writes and accepts that the PostToolUse hook auto-commits. Triggers on: fold the log, run a fold, run wiki-fold, log rollup, roll up log entries.

Ingest sources into the Obsidian wiki vault. Reads a source, extracts entities and concepts, creates or updates wiki pages, cross-references, and logs the operation. Supports files, URLs, and batch mode. Triggers on: ingest, process this source, add this to the wiki, read and file this, batch ingest, ingest all of these, ingest this url.

Health check the Obsidian wiki vault. Finds orphan pages, dead wikilinks, stale claims, missing cross-references, frontmatter gaps, and empty sections. Creates or updates Dataview dashboards. Generates canvas maps. Triggers on: "lint", "health check", "clean up wiki", "check the wiki", "wiki maintenance", "find orphans", "wiki audit".

Answer questions using the Obsidian wiki vault. Reads hot cache first, then index, then relevant pages. Synthesizes answers with citations. Files good answers back as wiki pages. Supports quick, standard, and deep modes. Triggers on: what do you know about, query:, what is, explain, summarize, find in wiki, search the wiki, based on the wiki, wiki query quick, wiki query deep.

Claude + Obsidian knowledge companion. Sets up a persistent wiki vault, scaffolds structure from a one-sentence description, and routes to specialized sub-skills. Use for setup, scaffolding, cross-project referencing, and hot cache management. Triggers on: "set up wiki", "scaffold vault", "create knowledge base", "/wiki", "wiki setup", "obsidian vault", "knowledge base", "second brain setup", "running notetaker", "persistent memory", "llm wiki".

Use when allocating PPA budgets top-down to submodules. Triggers on 'PPA', '预算', 'budget', '面积分配', '功耗分配', '性能分配', 'PPA拆解', '预算闭合'. Decomposes system-level PPA targets to submodule budgets and verifies closure.

Use when standard CBB cannot fully meet requirements and user confirmation is needed. Triggers on 'CBB例外', 'CBB差异', '复用还是自研', 'CBB exception', 'CBB confirm'. Lists differences item by item and confirms reuse vs custom development with user.

Use when designing clock domain crossing architecture. Triggers on 'CDC', '跨时钟域', '时钟域', '同步策略', '多时钟', 'clock domain', '亚稳态', '双触发器'. Performs multi-clock domain partitioning, CDC signal identification and synchronization strategy design.

Use when exploring PPA design space for optimal solutions. Triggers on '设计空间', 'DSE', '帕累托', 'pareto', 'PPA探索', '方案比选', 'trade-off', 'design space'. Performs Area-Performance-Power 3D exploration to find Pareto-optimal set.

Use when generating chip module diagrams (block diagrams, timing diagrams, FSM diagrams). Triggers on '框图', '时序图', '状态机图', 'diagram', '架构图', '画图', '画一个'. Generates module block diagrams, timing diagrams and state machine diagrams. Primary format: D2→PNG for block/FSM diagrams, Wavedrom→PNG for timing diagrams.

芯片架构文档多维度评分器。对 FS 功能规格书、UA 微架构文档、RTL 代码进行 10 维度量化评分（总分100），集成跨文档一致性检查、风险加权评分、自动改进建议生成和评分→改进→复评闭环。支持单文档评分、批量评分、版本对比、闭环改进。触发词：'文档评分','文档打分','FS评分','UA评分','RTL评分','代码评分','架构评分','质量评分','doc score','文档质量检查','评分报告','评分改进','文档质量闭环'.

Use when designing microarchitecture document structure. Triggers on '文档结构', '章节设计', 'doc structure', '文档模板', '内容权重', '文档组织'. Designs chapter structure and content weight allocation for microarchitecture specifications.

Use when verifying RTL implementation deliverables completeness before delivery. Triggers on '交付', 'delivery', '交付物', '交付清单', '完整性检查', 'deliverables'. Validates all deliverables exist and pass quality gates, outputs delivery checklist.

Use when checking RTL implementation input completeness before coding. Triggers on '输入确认', 'input triage', '输入检查', '文档完整性', '输入分类', 'input check'. Checks microarch docs, coding style, CBB list completeness and selects execution path.

Use when planning RTL module structure from microarchitecture docs. Triggers on '模块结构', '端口列表', '子模块划分', '文件清单', 'module structure', 'port list'. Extracts ports, submodule partitioning and file list from microarch docs.

Use when running parallel RTL development across multiple submodules. Triggers on '并行开发', 'parallel', '多模块并行', '并行subagent', 'parallel dev', '并行调度'. Coordinates Plan Mode analysis, parallel subagent dispatch, top-level integration and PR confirmation.

Use when running lint checks, synthesis, or quality gates on RTL code. Triggers on '综合', 'lint', 'synth', 'quality gate', '质量门禁', '门禁', 'verilator', 'yosys', '自检', 'check'. Executes lint+synth checks with auto-heal loop on failures.

Use when implementing RTL code for chip submodules. Triggers on 'RTL实现', 'rtl coding', '写rtl', '代码实现', '数据通路', '控制逻辑', 'rtl code'. Implements data path, control logic, CBB integration and interface per submodule, strictly following architecture freeze.

Use when generating SDC constraints, SVA assertions or testbench for RTL. Triggers on 'SDC', 'SVA', 'testbench', '时钟约束', '断言', 'TB', '约束文件', 'assertion'. Generates clock constraints, SVA assertions and testbench based on microarch timing strategy.

Use when performing final self-check on RTL implementation before delivery. Triggers on '自检', 'self-check', 'self check', '实现自检', 'quality checklist', 'IC-01', 'IM-01', '检查清单'. Runs IC-01~39 + IM-01~08 implementation quality checklist.

Use when defining module interface contracts. Triggers on '接口契约', 'interface contract', '信号列表', '接口定义', '端口定义', '接口时序'. Defines signal list, timing, protocol behavior and SVA for module interfaces.

Use when designing low-power architecture for chip modules. Triggers on '低功耗', 'UPF', '功耗域', 'power domain', 'isolation', 'retention', 'clock gating', 'power gating'. Designs power domain partitioning, isolation/retention strategy and UPF.

Use when generating microarchitecture charts (D2, Wavedrom, Interface diagrams). Triggers on '图表生成', 'chart workflow', 'D2编译', 'wavedrom编译', '接口图', '图表工作流', 'generate charts'. Orchestrates D2/Wavedrom/Interface chart generation, compilation and validation.

Use when generating D2 architecture diagrams, data flow diagrams, or FSM state machine diagrams. Triggers on 'd2', '架构图', '框图', '状态机图', 'diagram', '数据通路图', 'generate d2', '模块连接图'. Compiles .d2 source to PNG using dagre layout.

Use when generating interface port PNG diagrams from Verilog module declarations. Triggers on '接口图', '端口图', 'interface gen', 'port diagram', '接口PNG', 'module snapshot'. Generates module_snapshot style port PNGs with inputs on left, outputs on right, signal names with width and direction arrows.