memory-layout

name	memory-layout
description	This skill should be used when the user asks about "flash sectors", "flash pages", "SRAM regions", "SRAM layout", "linker script", "memory map", "CCM RAM", "DTCM ITCM", "backup SRAM", "external memory", "FMC", "FSMC", "SDRAM configuration", "memory-mapped peripherals", "base addresses", or needs to define or understand STM32 memory organization for linker scripts or memory allocation.
version	1.0.0

Memory Layout Extraction

Extract Flash, SRAM, and peripheral memory organization from reference manual and datasheet PDFs for use in linker scripts and memory-aware code.

What to Extract

Flash Memory

• Base address (always 0x08000000 on STM32)
• Total size
• Organization: sectors (F2/F4/F7: variable size) or pages (F0/F1/F3/L4/G0/G4: uniform size)
• Sector/page sizes and addresses
• Dual-bank support (if available)
• OTP (One-Time Programmable) area location and size

SRAM Memory

• SRAM1 base address (0x20000000) and size
• SRAM2 (if present): base address and size
• SRAM3 (if present): base address and size
• CCM (Core Coupled Memory) on F3/F4: base address (typically 0x10000000), size, restrictions (no DMA access)
• DTCM/ITCM on F7/H7: addresses, sizes (zero-wait-state access)
• Backup SRAM: base address, size (battery-backed, retained in VBAT mode)

Peripheral Memory

• Peripheral base addresses (0x40000000 region)
• APB1, APB2, AHB1, AHB2 peripheral base addresses
• Cortex-M internal peripherals (0xE0000000): NVIC, SysTick, SCB, MPU, FPU

External Memory (if FMC/FSMC present)

• FMC/FSMC base addresses for each bank
• Bank 1 (NOR/SRAM): 0x60000000-0x6FFFFFFF
• Bank 2 (NAND): 0x70000000-0x7FFFFFFF
• Bank 3 (NAND): 0x80000000-0x8FFFFFFF
• SDRAM Bank 1/2: 0xC0000000/0xD0000000

Where to Find This Information

Reference Manual - Memory Map

Glob pattern: docs/reference-manual/*.pdf

1. Read pages 1-5 (ToC)
2. Find "Memory and bus architecture" or "Memory organization" (typically chapter 2)
3. This chapter contains:
   • Global memory map figure (address ranges for all regions)
   • Flash memory organization table (sector/page addresses and sizes)
   • SRAM regions and their addresses
   • Peripheral register boundary addresses

Reference Manual - Flash Chapter

1. Find "Embedded Flash memory" chapter in ToC
2. Contains detailed Flash organization: sector sizes, addresses, erase granularity
3. Important for linker script Flash region definition

Datasheet - Memory Map Summary

Glob pattern: docs/datasheet/*.pdf

1. Search for "Memory map" table (usually a compact summary)
2. Shows Flash/SRAM sizes for the specific variant
3. May differ between variants in the same family (e.g., different Flash sizes)

Reference Manual - FMC/FSMC (if external memory used)

1. Find "Flexible memory controller" or "FMC" chapter
2. Contains external memory bank configuration registers
3. SDRAM timing register configuration

Extraction Process

1. Glob docs/reference-manual/*.pdf
2. Read ToC to find memory organization and Flash chapters
3. Read memory map section - extract address ranges for all regions
4. Read Flash organization - extract sector/page sizes and addresses
5. Read SRAM section - extract all SRAM region addresses and sizes
6. Check for FMC/FSMC chapter if external memory is needed
7. Optionally read datasheet memory map for variant-specific sizes
8. Generate linker script memory regions from extracted data

Linker Script Generation

From extracted memory data, build the MEMORY{} block:

MEMORY
{
  FLASH  (rx)  : ORIGIN = 0x08000000, LENGTH = [extracted flash size]
  SRAM1  (rwx) : ORIGIN = 0x20000000, LENGTH = [extracted sram1 size]
  SRAM2  (rwx) : ORIGIN = [extracted addr], LENGTH = [extracted size]
  CCM    (rwx) : ORIGIN = 0x10000000, LENGTH = [extracted ccm size]   /* if present */
  BACKUP (rwx) : ORIGIN = [extracted addr], LENGTH = [extracted size]  /* if present */
}

Stack and heap definitions:

_Min_Heap_Size  = 0x200;   /* 512 bytes minimum heap */
_Min_Stack_Size = 0x400;   /* 1024 bytes minimum stack */

Key Concepts

CCM Restrictions (F3/F4)

CCM RAM is connected directly to the CPU D-Bus. DMA controllers CANNOT access CCM. Place DMA buffers in SRAM1/SRAM2 only. Use CCM for stack, local variables, or non-DMA data.

DTCM/ITCM (F7/H7)

Zero-wait-state access from CPU. DTCM for data, ITCM for code. DMA cannot access TCM on most variants. Place performance-critical code in ITCM, critical data in DTCM.

Backup SRAM

Retained when VDD is off but VBAT is powered. Must enable PWR clock and set DBP bit to access. Useful for storing configuration across power cycles.

Additional Resources

• references/memory-extraction-guide.md - Memory map patterns per family, linker script templates, Flash sector tables