| name | generate-pcb-design |
| description | Produce a PCB design starting point from a project's BOM and wiring spec — schematic netlist, board stack-up and layout guidance, and ESP32-specific rules (antenna keep-out, strapping pins, decoupling). Output is KiCad/EasyEDA-ready design input, not finished Gerbers. |
Generate PCB Design
Take a project from "wired on a breadboard" to "ready to lay out a board".
Inputs
- Project slug →
bom.json, wiring.md (run generate-wiring-diagram-spec first if missing), datasheets/*.md for footprint/pinout details.
- Ask up front: module-carrier board (dev boards / breakouts soldered onto a carrier PCB — the usual hobbyist choice) or bare-IC design? Default to module-carrier; a bare-chip ESP32 layout (RF matching, impedance control) is expert territory — say so and keep the scope honest.
Output
Create <projects_dir>/<slug>/pcb/:
1. netlist.md
Every net, derived from the wiring spec: net name, class (power / ground / signal / high-speed / analog), and the pin of every part on it. This is the authoritative connectivity handoff — formatted so it can be re-entered in KiCad's schematic editor or EasyEDA without ambiguity.
2. schematic.md
A block-level schematic as a mermaid diagram (modules as nodes, buses as labelled edges) plus per-block notes: pull-ups with values, decoupling caps per datasheet, series resistors, protection (TVS on external connectors, reverse-polarity on battery input).
3. layout-notes.md
- Board: suggested outline dimensions, 2-layer default, mounting holes, connector edge placement.
- ESP32 rules: PCB antenna keep-out (no copper under/beside the antenna end, module at board edge), strapping pins kept free of pull-downs at boot, EN pin RC delay.
- Power: star or plane grounding, regulator placement, trace widths for the computed rail currents.
- Noise: analog sensors away from switching regulators and radio; I2C length limits.
- Fab notes: default to JLCPCB/PCBWay conventions (min trace/space, via size) unless the user names a fab.
Hand-off
Recommend a tool path by user preference: KiCad (open-source, local) or EasyEDA (browser, direct JLCPCB order flow). Offer generate-mockups for a rendered visual of the assembled board. This skill deliberately stops before actual layout — routing decisions belong in the EDA tool with the real footprints loaded.
