菜单
Produce a PCB design starting point from a project's BOM and wiring spec — schematic netlist, board stack-up and layout guidance, and ESP32-specific rules (antenna keep-out, strapping pins, decoupling). Output is KiCad/EasyEDA-ready design input, not finished Gerbers.
默认使用会先检查来源的 Prompt；你也可以切换为直接命令，或下载本地副本。
决定是否安装前，请先阅读 SKILL.md，以及 SkillsMP 当前展示的配套文件。
用 Codex 或 Claude 帮你安装 复制这段 Prompt，粘贴到 Codex、Claude 或其他助手里，让它检查 Skill 页面并帮你完成安装。
直接命令不会经过审查 Prompt；运行前请先检查来源。
npx skills add https://github.com/danielrosehill/Claude-Hardware-Spec-Assembly-Plugin --skill generate-pcb-design命令会保持在同一行。复制前请横向滚动并检查完整内容。
想先保存到本地？可下载 SkillsMP 当前能够提供的文件。
Build a structured hardware specification and BOM for a project. Walks the user through goals, constraints, and functional requirements, then produces a markdown spec plus a structured BOM (parts, quantities, rationale) saved into the project directory.
Estimate the total cost of a project's BOM. Reads bom.json from a project, applies typical price ranges per vendor (informed by the user's preferred suppliers and location), and produces low/mid/high cost envelopes plus shipping considerations.
Produce a textual wiring specification — pin map, connection table, and power distribution — suitable for handoff to a diagram tool (Fritzing, KiCad, Wokwi, draw.io) or for direct use during breadboarding. Not a graphical diagram itself.
基于 SOC 职业分类
正在显示 SKILL.md
| name | generate-pcb-design |
| description | Produce a PCB design starting point from a project's BOM and wiring spec — schematic netlist, board stack-up and layout guidance, and ESP32-specific rules (antenna keep-out, strapping pins, decoupling). Output is KiCad/EasyEDA-ready design input, not finished Gerbers. |
Take a project from "wired on a breadboard" to "ready to lay out a board".
bom.json, wiring.md (run generate-wiring-diagram-spec first if missing), datasheets/*.md for footprint/pinout details.Create <projects_dir>/<slug>/pcb/:
netlist.mdEvery net, derived from the wiring spec: net name, class (power / ground / signal / high-speed / analog), and the pin of every part on it. This is the authoritative connectivity handoff — formatted so it can be re-entered in KiCad's schematic editor or EasyEDA without ambiguity.
schematic.mdA block-level schematic as a mermaid diagram (modules as nodes, buses as labelled edges) plus per-block notes: pull-ups with values, decoupling caps per datasheet, series resistors, protection (TVS on external connectors, reverse-polarity on battery input).
layout-notes.mdRecommend a tool path by user preference: KiCad (open-source, local) or EasyEDA (browser, direct JLCPCB order flow). Offer generate-mockups for a rendered visual of the assembled board. This skill deliberately stops before actual layout — routing decisions belong in the EDA tool with the real footprints loaded.